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Optically isolating an I2C interface

24 Apr 2012  | Eric D. Blom, Senior Design Engineer, IXYS-Clare Inc.

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The I2C bus is a set of hardware and software rules that allows communication between multiple devices over a shared, two-wire interface. In operation, the bus uses one line (SDA) for data and another line (SCL) for the clock. In standard mode (up to 100kbps) or fast mode (up to 400kbps), each of the two wires can be pulled high through an external pull-up resistor. Thus, if any of the multiple open drain devices asserts a logic low onto either line of the bus, the logic low is seen at all devices. Rules defining master and slave devices determine who is allowed to drive the bus lines, and when. The bus specifications were defined and are maintained by NXP Inc.

The device that is acting as the bus master drives the clock line (SCL) when communicating with slave devices. Any addressed slaves respond at a time defined by this clock by asserting the data (SDA) line using a specified protocol. The simplest system contains only one master device with all other devices always responding as slaves. In more complex systems multiple devices can take turns being bus master, and the SCL line will be driven by whichever device is master at that time. There are many applications requiring ground isolation or logic-level translation between devices where the simple I2C protocol is very useful. The small number of wires (two) minimizes the number of isolators and keeps down the cost of isolated systems, although each direction of the wire has required its own isolator.

Systems in which the bus can be isolated such that only slave devices exist on one side of the isolation barrier do not need bidirectional isolation of the SCL line. A bus containing only I2C slaves that do not implement clock stretching (to slow down the bus to the speed required) does not need bidirectional isolation of the SCL line. Simplified isolators, with one bidirectional path (for SDA) and one unidirectional path (for SCL), may be used in such systems (see Figure 1).

Figure 1: The CPC5902 provides bidirectioal isolation on both SCL and SDA while CPC5903 is bidirectional only on SDA.

Systems in which devices on either side of the isolation barrier may function as bus master need bidirectional isolation of both lines. The fully bidirectional system supports all possible variations: it can be operated with a single master, with clock stretching slaves or with master devices taking turns on both sides. Thus, it is the recommended configuration if unknown future devices will be later added to the bus.

The propagation delay of an optoisolated unidirectional bus line does not generally cause unexpected consequences. However, operation of isolated bidirectional lines with real world propagation delays will require nonstandard logic levels and generate unexpectedly complicated results when operated under not-unexpected conditions as will be shown.

Isolating a bidirectional open-drain bus

The I2C bus, which contains at least one bidirectional open-drain bus, does not easily lend itself to optical or other isolation. The ideal bus model of the SDA line is a shared pull-up resistor connected to bidirectional I/O pins at multiple devices. The bidirectionality of the bus in an isolated bus system causes a departure from this ideal model. If a real-world active bus repeater or isolator drives its own input low at both I/O pins, then it latches the first logic low asserted, and allow no further activity.

Figure 2: This bus repeater will latch its I/O pins low.

Figure 3: This bus repeater without latch protection goes low and is stuck low at IOA and IOB.

One way to avoid the latch-up problem is to use a separate input and output pin on all devices at Side B. When the repeater output is driven low it does not drive the repeater input low. There are peripherals, which are intentionally designed to run with standard optoisolators, that utilize this extra wire to provide separate data input and output wires at devices at Side B. This does require an extra package pin, and prohibits the use of most I2C devices (without the extra pin) at the isolated Side B bus. This complicates debugging of the bus because most I2C bus analyzers do not have provision for the third wire, and can be used on Side A of the isolated bus.

Figure 4: This circuit avoids bus latching by using an extra pin to implement a separate input and output at Side B.

A different method of bus logic low latch-up prevention is used in the CPC5902 and CPC5903, and by some other bus repeaters and isolators. This method uses non-standard three-level logic at the isolated Side B. This method only requires two wires, and works with all I2C devices and bus analyzers. It also works with the separate data-in/data-out pin devices if the data-in and data-out pins are shorted together at Side B.

Figure 5: This circuit uses three-level logic with no extra pins to implement bus latch protection.

The repeater output cannot drive its own input low if the repeater output driver is designed such that it can only drive VOLB down to 0.23*VDD. The same is the case when the receiver input threshold, VILB, is designed to switch near 0.2*VDD. The I2C specification defines VIL to be any input voltage below 0.3*VDD. All devices attached to the bus that meet this spec will correctly see the non-standard output level, VOLB, as an asserted logic low. When using this, a careful designer must pick the value of pull-up resistors on Side B of the bus such that devices on that bus can drive lower than VILB=0.2*VDD. This may require picking a slightly higher value pull-up resistor.

As an example, consider a system in which there are both 3mA-drive I2C standard-mode devices and 6mA-drive I2C fast-mode devices on the isolated Side B of the bus. The pull-up resistor value in a usual system must be picked so that the standard-mode (weakest) device will pull the bus lower than 0.3*VDD when asserted low. However, the pull-up resistor must be picked so the weakest device will pull lower than 0.2*VDD when used at Side B of the CPC5902 and CPC5903 isolators, as described below.

Three-level system pull-up resistor selection
If the VDDB supply voltage is 3V to 3.6V, the minimum value of the pull-down resistance for standard levels is that value that pulled the bus below 0.3*VDD when VDDB=3.6V. At 3.6VDD, 0.3*3.6=1.08V, and 3.6V to 1.08V=2.52V, must drop across the pull-up resistor when the minimum guaranteed output drive of 3mA is applied. Thus, the minimum value of resistor for this standard-level, standard-mode system is 2.52V/3mA=840ohms. The designer needs to pick a standard value which is slightly greater than this; how much greater depends on the guaranteed resistor tolerance and the amount of desired noise margin. A reasonable minimum value might be 866ohms for 1% tolerance resistors.

For the CPC5902 and CPC5903 non-standard level Side B, for VDDB between 3V and 3.6V, use the same method, but require that the bus pull down to 0.2*VDDB when VDDB=3.6V. At 3.6VDD, 0.2*3.6=0.72V and 3.6V-0.72V=2.88V, which must drop across the resistor when the 3mA minimum drive is applied. Thus, the minimum value of resistance for the CPC5902 and CPC5903 family when there are 3mA drive devices on the side B bus is 2.88V/3mA=960ohms. A standard value of 1% tolerance resistor that will stay above this minimum is 976ohms. Thus, in this example, the use of CPC5902 or CPC5903 requires a 976ohm RPULLUP to guarantee operation under all conditions, while a standard level implementation would have required 866ohms.

Note that I2C fast-mode-capable devices guarantee 6mA of output drive, and could use smaller resistors. However, the presence of the 3mA drive standard mode devices on Side B of the bus make the larger resistance mandatory to insure their operation. Manufacturers design their standard mode output drivers to supply more than the required 3mA of the I2C-specification, and the minimum values picked are then reasonable choices for actual specified values.

Also note that the side using nonstandard three level logic on any isolator cannot be connected to another device using nonstandard three level logic. For example, SideB of one CPC5902 or CPC5903 cannot be connected to Side B of another CPC5902 or CPC5903 if communication of one through the other is required. This is because the output logic low of one will not be seen as a valid logic low at the input of the other. Side B of isolators can be connected to Side A of more isolators if cascaded operation is desired.

Time delays in bus repeaters and isolators
Another way in which an isolated bus system departs from the ideal pull-up resistor model is in the timing of transmitted versus received data. There is little time delay between when devices on the bus level that goes to an asserted logic low or return high for a non-isolated system of multiple devices. Delays can exist within isolators, and such delays must be carefully accounted for to insure legal values of specifications such as data setup and data hold times.

The LED-photodetector cascade within an optoisolator is inherently a lowpass filter. The primary bandwidth limitation is usually capacitance at the photodetector, which must be charged and discharged by the small photo-generated current. In a logic optoisolator, this electro-optical filter is then followed by a comparator. This low-pass filter suppresses very short logic pulses, and adds a time delay to any logic signal applied. Later sections of this paper will show that the effects of this filter on pulse-widths and delays can be modified by using different latch-up suppression methods.

A simple, buffered RC filter is used here to model the low-pass characteristic, and a pair of logic inverters are used to model the high-gain comparator (see Figure 6). This circuit is used elsewhere in this paper as a circuit block named "Filtered 60ns Delay."

Figure 6: A filtered 60ns delay circuit is used to model optics with propagation delay followed by a comparator.

For applied pulse-widths greater than five times the RC time constant (5RC) at Node "RC," this circuit exhibits nearly the same filtering for going-low and going-high signals. For example, the "Filtered 60ns Delay" circuit delays the rising edge of a 400ns pulse by 60ns and the falling edge by 78ns. The small asymmetry is because the comparator switching threshold voltage is lower than VDD/2.

An asymmetry exists in real logic optoisolators when the capacitance at the photodetector is charged quickly by photocurrent from an over-driven LED, but can self-discharge at a lower rate.

However, a low-pass filtered comparator is a non-linear circuit even for digital signals. When applied after a "long" (greater than 5RC) wait, a short pulse will ramp Node RC up from zero to the comparator switching threshold voltage (see Figure 7). If the pulse width is not greater than or equal to 5RC, the Node RC does not ramp to VDD after the rising edge is applied (see Figure 8). Thus, when the falling edge arrives and the Node RC starts to go negative, it does not need to drop all the way from VDD down to the comparator threshold.

Figure 7 below shows the Node RC charging all the way to VDD for a nominal input pulse. The going-low delay is similar to the going-high delay, and the output pulse is only slightly stretched compared to the pulse at its input.

Figure 7: For a pulse longer than 400ns, the going-low delay is 77.5ns.

Figure 8 below shows the Node RC barely charging up to the comparator threshold voltage, and quickly going below it when the falling edge starts to pull Node RC negative. It shows the two problems that should be addressed in a robust isolator design:

1. when very short pulses are applied, the tPHL delay becomes much shorter than the delay for longer pulses;

2. the output pulse-width, which is lengthened for long pulse-widths, is severely shortened for short applied pulses.

Figure 8: For a 60ns applied pulse, the going-low delay is only 13ns.

This table shows the tPLH, tPHL and output pulse-width vs input pulse-width at "Filtered 60ns Delay" for a pulse applied after 5RC or longer of stable setup.

Note that in the optoisolator designs to be shown in later sections, there is a logical inversion before the input to the Filtered 60ns delay and another after its output. This alters the effect of the pulse distortion as the tPHL (not tPLH) at the IO pins remains constant. The tPLH (not tPHL) at the IO pins is the delay which is greatly affected by applied pulse duration after sufficient setup. For I2C applications, this is generally a preferred topology as valid "long" asserted low pulses are slightly stretched instead of being slightly shaved.

The next sections will show the effects of adding the Filtered 60ns Delay at all the optical interfaces of various optoisolator topologies. In order to maximize simulated bus bandwidth, assume only 20pF of total load capacitance and fast-mode compatible 499ohm pull-up resistors to 3.3V at all IO pins. An asserted low pulse of varying duration will be applied at Side B and the resulting pulses at both Side A and Side B will be compared.

Bus devices utilizing separate SDA in and SDA out method
Devices which use the separate SDAin and SDAout pins topology for latch-up avoidance are meant to be used with standard unidirectional logic optoisolators. When the optics are replaced with Filtered 60ns Delay blocks, the effects on pulses of various lengths can be examined.

Figure 9: Separate SDAin/SDAout circuit pulse-shaves applied signals of duration close to the propagation delay.

The I2C specification for fast-mode operation requests that internal filtering at devices on the bus suppress pulses of less than 50ns. Note that the isolators themselves are not "on" the bus, they "are" the bus, and thus they do not have to perform this suppression. The devices attached to the isolators are supposed to suppress the glitches. However, the isolator can either help or hurt glitch suppression. In the table above, glitches less than 55ns applied at IB do not propagate at all to IOA or OB; for very short pulses this isolator aids in glitch suppression.

However, when the applied pulse length gets to 57ns, less useful effects begin to appear. The optics have shaved the width of the applied pulse: a 57ns pulse applied at IB yields only a 5.5ns pulse at IOA. Instead of helping in glitch suppression, the filtering within the optics is now causing glitching at IOA when a non-glitch pulse has been applied at IB.

Figure 10: An applied pulse of 82ns at IB results in an 8ns pulse at OB.

As the pulse width is increased to 80ns, the pulse at IOA grows to 57.4ns in length. Additional filtering of the A-to-B optics has so far suppressed all indication of pulsing at OB. Thus, the bus on the IOA side has seen one more negative edge and one more positive edge than the bus at OB. If this channel is being used for clock, then this can be a very serious problem.

At 82ns width, OB finally begins to get a pulse, but only an 8ns glitch. Again the optics has taken a more-legal 82ns pulse and made a glitch from it, this time at the OB port. Applied pulses near 100ns, the OB pulse grows to 64ns in length, and the same number of edges that were generated at IB will be seen at IOA and OB.

Simple three-level logic method

Simple non-standard three-level logic as a latch-up prevention method also suffers from glitch generation mechanisms. The worst path is when IOB is driven. This is because, unlike Side B, the isolator at IOA is allowed to drive its own input at IOA. The signal thus gets optically filtered going from B to A and then again going from A back to B.

Figure 11: A typical three-level circuit double pulses IOB for applied pulsewidths near the propagation delay.

In the table above, glitches less than 55ns applied at VIN do not propagate at all to IOA; so for very short pulses, this isolator aids in glitch suppression. Note that the VIN-driven open-drain driver is applied to IOB, but that capacitance at IOB causes the pulse width applied at VIN to grow by up to 6ns. When the applied pulse length gets to 57.5ns, the optics have shaved the width of the applied pulse. A 64ns pulse applied at IOB yields only an 8.7ns pulse at IOA. As the pulse-width grows, the output at IOA grows. When the output pulse-width at A is long enough to pass through the optical filter at A to B, the return signal causes an extra "echo" pulse at IOB. This extra set of edges at IOB continues until the pulse width applied at IOB is longer than two (2) optical turning-on delays. After that, the signal at IOB is stretched by the delayed echo, but this is not a problem, moderate amounts of pulse stretch are generally allowed by I2C timing specifications.

Figure 12: The typical three-level circuit with 83ns pulse applied generates an extra "echo" glitch of 8ns at IOB.

Three-level with pulse-stretch and self-drive method

To overcome the pulse-shaving and double-pulsing problems, CPC5902 and CPC5903 use a filtered, pulse-stretched, self-driven system with the three-level method on their bidirectional channels similar to Figure 13.

Figure 13: Additional circuitry is used to eliminate double pulsing.

Signals asserted by devices on the bus at IOB first encounter an input filter which rejects very short pulses. In the example circuit, this is shown as delay_25ns in series with the input at IOB. When using CPC5902 and CPC5903, the effective low-pass filtering of this block is improved by increasing CLOAD at the input. A delay of 25ns is used here to differentiate this filter from the optical filter.

Pulses applied to I/O at Side B (IOB), which are long enough to pass through the input filter, assert the signal FLOP_CLOCK_H. Assuming a short pulse generates a logic high at FLOP_CLOCK_H is applied, the brief logic high is routed through the OR gate to B to A optical channels for transmission. The presence of this "long enough to be legal" signal is also stored by the flip-flop.

Figure 14: Double pulsing at IOB is eliminated by the additional circuitry.

The stored signal is then applied to the non-standard output level driver at IOB, which normally drives the I/O to 0.23VDDB. Thus, the part self-drives its own input while it is already being driven by a device on the bus. Unlike the simplified drive circuit, the circuit used in CPC5902 and CPC5903 sink current, having little effect on the signal while driven below 0.2*VDDB by a device on the bus.

While self-driving the IOB port, the stored signal is also applied through the OR gate to the B to A optical channel. A short FLOP_CLOCK_H signal can return low, but the stored signal remains high. The OR gate at the input to the B to A optical filter insures that the optics will continue to be driven. This is until an edge is returned and the A to B optical filter clears the flip-flop. Thus, the drive into the B to A optics is stretched to a minimum length of two (2) optical turning-on delays.

As was shown in the simple three level case above, the minimum length of the stretched pulse is now always the minimum required to avoid double pulsing. Moreover, the stretched drive-pulse-width tracks the actual delays at the two optic filters, so that it is always of optimal length. This feedback can also be interpreted as an error reduction loop. The B to A optics continues to be driven until it has been verified by an A to B transmission that the data has successfully arrived.

Upon a turning-on edge being received at FROM_AH (see Figure 13), the flip-flop is cleared. Assuming that the device driving IOB has ceased externally driving it, then the drive into B to A is de-asserted. The de-asserted edge propagates through a B to A turning-off delay, then a delay determined by the RPULLUP*CLOAD at IOA. After an additional A to B turning-off delay, the deasserted edge becomes available at FROM_AH, and is used to deassert the drive at IOB. Thus the minimum pulse at IOB is:

(delay_on_BtoA) + (delay_on_AtoB) + (delay_off_BtoA) + (RCdelayA) + (delay_off_AtoB).

Note that for pulses long enough not to be suppressed by the input filter, there are always the same number of edges asserted at both sides of the isolator. As the applied pulse-width becomes longer than delay on B to A + delay on A to B, the pulse-width at IOA is no longer stretched by the flip-flop circuit. The pulse will be stretched slightly because the turning-on delay is shorter than the turning-off delay.

The pulse at IOB is then only stretched by a time determined by:

(delay_off_BtoA) + (RCdelayA) + (delay_off_AtoB)

Thus, for legal length I2C fast mode pulses (logic low longer than 1.3us), the flip-flop circuit is not used to stretch the drive to the optics. The flip-flop circuit and the self-drive circuit at Side B will stretch an applied legal pulse at IOB by an amount primarily determined by the turning-off optical delays as above. This pulse stretch is similar to what happens to pulses applied to a resistor-pulled-up bus with a large capacitive load. The I2C fast-mode specifications will tolerate stretches of a few hundreds of nanoseconds even at 400kbps rates, and will tolerate even more for smaller values of CLOAD.

Conclusion
The ideal model of an open-drain bus as a simple, shared pull-up resistor is no longer instantaneously valid when using bus isolators exhibiting real-world propagation delays. If the delays are not considered in hardware design, then glitching or the difference in the number of rising or falling edges at each isolated bus are possible. These occur when short pulses are applied.

The CPC5902 and CPC5903 isolated bus repeaters uses verification feedback from the standard level Side A back to the non-standard level Side B and self-drive of the Side B I/O. This eliminates glitching and ensures that the same number of clock edges are seen at both busses. This feature greatly reduces the probability of an undetected error in data transmission across the isolation barrier.

References:
NXP Semiconductor, "I2C-bus Specification and User manual" UM10204_3, June 2007.

About the author
Eric Blom has been designing analog and mixed signal integrated circuits for IXYS-Clare since 2007. Previous occupations include digitizing temperature sensor integrated circuit design and mixed signal ATE equipment design. He has more than 30 years experience and a dozen patents in mixed signal system design and test. He earned a BSEE from Worcester Polytechnic Institute and MS from The Gordon Institute at Tufts University.




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