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Does DDR skew balancing scare you?

21 May 2012  | Vineet Gupta, Swati Gupta, Naveen Raina, Sunit Bansal

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Skew balancing report

Table 1: Skew balancing report

Loopback: The clock is generated at ACPHY and output was a 2bit clock. It is important to mention that the PHYAC from Synopsys had the capability to provide 3bit clock. Case analysis was employed to enable the pad Loopback paths. Also, generated clock is declared at the PHY output. This clock is not part of the provided SDC, since it was intended to keep the Loopback constraints totally separate and controlled. Example of added constraints is given below:

create_generated_clock [get_pins i_mpe41_ddr3ss_phy/i_c6ddr3_phy32_wrapper/DWC_DDR3PHYAC_0/ck_do[1]] –name clk_ddr_1_gen_loopback -source [get_ports clk_ddr] -multiply_by 2 set_case_analysis 1 i_mpe41_ddr3ss_phy/i_c6ddr3_phy32_wrapper/c6ddr_padring_0/pd_LMI_ODT/LB

Since it is hard to manually debug these reports, some shell scripts were written to analyze the worst setup and worst hold for any of the endpoints in each corner.

timing analysis for Phy

Table 2: Timing analysis for Phy

Table II shows the worst setup and hold in all the corners. With this a call can be made is the hold and setup in the corner will be met. These do not necessarily belong to the same path, these are the worst setup and worst hold in that respective corner for that clock. Once it is ensured that convergence can be attempted, one can explore the specific corner reports and begin manual ecos.

Methodology for CTS

Figure 1: Methodology for CTS

Comparison of methodologies
Mainly two approaches were used in previous designs.

HF router: High frequency router was more of a manual approach. It used an automation through which a buffer was inserted in front of the pin and then all the signals were buffered with same number of buffers at regular intervals. The delays were matched using net delays as the constraint for router. The process was iterative owing to multicorner analysis. Equal number of buffers was used in all the paths so that delays do not vary much across the corners. But a lot of effort was involved in calculating the correct number of buffers to be placed as the design needed several Sign off iterations for closure. Also, the tool was depended heavily upon to route the nets such that the net delays added to buffer delay gave the desired skew.


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