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AMIQ outs new design-oriented features in DVT IDE

07 Jun 2012

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AMIQ EDA has unleashed new design-oriented features in its Design and Verification Tools (DVT) IDE. The company stated that these features enable design engineers to easily understand how a signal propagates in a design, connect two modules across the design hierarchy, and inspect and document a module structure.

The DVT IDE is a powerful and complete code development environment for the e language SystemVerilog, Verilog and VHDL, noted AMIQ. It increases the speed and quality of code development and simplifies the maintenance of reusable libraries and legacy code. DVT is built on the Eclipse Platform and comprises an IEEE standard-compliant parser, a smart code editor, and a complete suite of tools that help with code readability, navigation, task tracking, documentation and debugging. The DVT IDE integrates with all major simulators, revision control systems and bug tracking engines. It also supports the popular verification methodologies UVM, OVM and VMM.

The first of the newly released features—Trace Port Connections—allows users to understand how a signal propagates in a design. The signal that needs to be traced is highlighted in the design hierarchy tree in the Trace Connections View. Users can easily locate the signal source, operation called "trace drive," or the signal destination, operation called "trace load."

The second new capability—Connect Module Instances—helps connect two modules across the design hierarchy. Such an operation can be tedious and error prone. With DVT, adding all the required ports from the source (output) module to the destination (input) module across the design hierarchy becomes straightforward. Before performing the operation, a user can preview both the design structural changes and source code changes.

A third capability—Module Diagrams—is similar to the DVT's popular UML diagrams, which allows verification engineers to inspect classes. Module Diagrams allows designers to inspect and document the structure of a module by showing a module's direct submodules, the connections between them and the connections to the module's ports. The diagrams are always synchronized and directly linked with the source code.




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