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Powering DDR memory and SSTL

01 Dec 2011  | Peter James Miller

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The most common DRAM in modern electronics is SSTL (stub-series-terminated-logic)-driven DDR (double-data-rate) memory. Conventional logic and I/Os use standard system bus voltages; however, DDR-memory devices need the precision that only local POL (point-of-load) regulators can provide. For sufficient noise margin, two of the five system supply voltages must reference other voltages. These are the I/O VDD (drain-to-drain voltage), the VDDQ (drain-to-drain core voltage), the VDDL (drain-to-drain logic voltage), the VTTREF (termination-tracking reference voltage), and the high-current-capable midrail VTT (termination-tracking voltage).

VDDQ: the simplest supply rail
Most DDR-memory devices use a common supply for core, I/O, and logic voltages; these terms are commonly combined and referred to as VDDQ. Current standards include 2.5V for DDR and DDR1, 1.8V for DDR2, and 1.5V for DDR3. DDR4, which should debut in 2014, will have a voltage of 1.05 to 1.2V, depending on how far the technology advances before the release of the standard.

DDR memory's VDDQ is the simplest supply rail. A variety of POL power sources can supply most DDR-memory devices because they allow 3% to 5% tolerance. Single-chip, onboard memory for small embedded systems might require only a linear regulator to provide 1A or 2A of current. Large multichip systems or small banks of DDR modules typically require several amps of current and demand a small switch-mode regulator to meet efficiency and power-dissipation needs. Large multimodule banks, such as high-performance processing systems, large data-logging applications, and testers, may demand 60A or more of VDDQ, driving designers to develop processor-core-like, multiphase power supplies just to meet memory needs.

Although a conventional converter can typically support VDDQ, it generally requires prebias support and the ability to regulate through high-speed transients as the memory switches states. No defined standard exists for prebias support, but it implies that the POL converter providing the VDDQ must prevent sinking current from the VDDQ supply if any voltage is stored on the VDDQ bypass and output capacitors during VDDQ power-up. This requirement is critical because SSTL devices contain parasitic and protection diodes between VDDQ and other supply voltages; VDDQ can damage these diodes if it sinks current through them during startup.

High-speed memory cells rapidly switch states. A memory chip or a module may change from low-intensity sleep, standby, or self-refresh states to a highly demanding read-write cycle in just a few clock cycles. This rapid switching places another strong demand on the POL supply providing the VDDQ. VDDQ supplies should switch from only 10% of their maximum load current to 90% in 1 to 2µsec. An array of small, local bypass capacitors near each VDD, VDDQ, and VDDL input typically provides faster, cycle-by-cycle transitions to the memory device. The combination of large output capacitors and high-speed control loops provides for sustained mode transitions and meets the tight accuracy requirements of DDR memory.

VTTREF realizes wider noise margins
Whereas VDDQ is a high-current supply that powers the core, the I/O, and the logic of the memory, VTTREF is a low-current, precision reference voltage that provides a threshold between a logic high (one) and logic low (zero) that adapts to changes in the I/O supply voltage. By providing a precision threshold that adapts to the supply voltage, VTTREF realizes wider noise margins than those possible with a fixed threshold and normal variations in termination and drive impedance. Specifications vary from device manufacturer to manufacturer, but the most common specification is 0.49 to 0.51 times VDDQ and draws only tens to hundreds of microamps.




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