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Solving design issues with JESD204B

27 Nov 2012  | Thomas Neu

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The 'B' revision of JESD204 standard increased the maximum data rate to 12.5Gbit/s with different amplitude and timing requirements for 3.125, 6.25 and 12.5Gbit/s. Furthermore, harmonic clocking was introduced where converters can be clocked with a higher order multiple of the sampling rate (such as by two, four and eight times). Clock dividers inside the converter generate the correct sampling clock rate while the system reference signal ensures the different clock phases get reset to a known, deterministic state so that the correct phase is used to maintain system synchronisation.

Given that the JESD204B seems to become the new digital interface industry standard of choice for both high-speed ADCs and DACs. Hence, system designers should be aware of both advantages and disadvantages it contains.

Figure 1: JESD204B simplifies the digital data interface and with subclass 1 multiple TI data converters are easily synchronised.

Advantages
 • Simplified board routing with much fewer lanes to route. As table 1 shows, by transitioning a dual 16bit ADC (such as the ADS42JB69) from a DDR LVDS interface to JESD204B, the output data bus reduces from 34 lanes to six lanes (20x mode) or ten lanes (10x mode). Using less board space translates into material cost savings as well as ability to shrink the overall product form factor.
 • It eliminates the need for data bus line matching for maximum setup and hold times. Managing the skew and timing match across 16 differential pairs at 500Mbit/s of a DDR LVDS dual 16bit 250 Msps ADC can become challenging, especially with interconnects longer than just one to two inches.
 • By using the deterministic latency feature, an entire system can be synchronised, enabling large scale data acquisition systems. The JESD204B standard provides three classifications based on the way the LMFCs within TX and RX devices are aligned to each other:
1. Subclass 0 – No support for deterministic latency (backward compatible with JESD204A).

2. Subclass 1 – SYSREF signal is used to align LMFCs within TX and RX devices.

3. Subclass 2 – SYNC signal is used to align LMFCs. No SYSREF signal exists.

Employing subclass 1 for example, the sampling instance between multiple devices can be aligned independent of bus trace length. Important to remember is that the SYSREF signal itself, as well as the individual device clocks, still need to be matched in length so that the LMFC is started simultaneously in all devices (figure 1).

 • Device pin count is reduced, enabling the use of much smaller packages for ADCs and DACs and processors/FPGAs, which may bring additional cost savings.
 • The 8b/10b encoding ensures a DC balanced data stream, which means transmission of equal amount of 0s and 1s allowing AC coupling of the interconnect. This eliminates the need for a standard, fixed common-mode voltage and provides a lot of freedom of SERDES design architectures. Additionally, the different control characters of the 8b/10b coding table are used to enable receiver synchronisation as well as lane and frame alignment.
 • It is easier to scale the data converter resolution. Since all output data is getting serialised over the same differential pairs, for example switching from a converter with a 14- to a 16bit resolution (or vice versa), doesn't require additional lanes to handle the data.
 • JESD204B eliminates the need for providing the exact required clock frequency to each device in the system. The harmonic clocking feature for example, provisions that a 250 Msps ADC can be operated with a 1GHz clock. The correct phase of the internal clock dividers is set by the SYSREF signal, ensuring system synchronisation.

Potential disadvantages
 • As the serial data rates increase beyond 3.2Gbit/s, more efforts are required to ensure signal integrity is maintained. Designing for 2.5 or 3.2Gbit/s may be relatively trivial, but a 7.5 or even 12.5Gbit/s link requires extensive simulation, PCB analysis, and possibly even a 3D field solver.
 • Compensation for signal amplitude loss, which increases with faster data rates, may require better (more expensive) PCB material.
 • Faster FPGAs, potentially, may be more expensive.
 • Depending on process node and implementation, the power consumption of the SERDES interface may be higher than the parallel LVDS or DDR LVDS implementation. In order to handle the faster data rates, transmitters get outfitted with pre-emphasis which boosts the signal amplitude; while receivers get outfitted with receive equalisation to recover data even from a seemingly completely closed eye.

JESD204B building blocks
The JESD204B interface contains four basic building blocks, which are common for a high-speed ADC or DAC.

Figure 2: JESD204B interface block diagram.


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