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FPGA-adaptive embedded software toolkit unveiled

26 Dec 2012

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The development of a DS-5 embedded software development toolkit with FPGA-adaptive debug capabilities for Altera SoC devices, which is a joint project between programmable logic company Altera Corp. and processor designer ARM, has recently been revealed.


The ARM Development Studio 5 (DS-5) Altera Edition toolkit is designed to remove the debugging barrier between the integrated dual-core CPU sub-system and FPGA fabric in Altera SoC devices. By combining the most advanced multi-core debugger for the ARM architecture with the ability to adapt to the logic contained in the FPGA, the new toolkit provides embedded software developers an unprecedented level of full-chip visibility and control through the standard DS-5 user interface. The new toolkit will be included in the Altera SoC Embedded Design Suite and will begin shipping in early 2013.
"Disruptive, innovative silicon devices demand equally disruptive and innovative software tools. That demand has been met by this innovative toolkit for Altera 28 nm Cyclone V and Arria V SoC devices and for upcoming Altera 20 nm SoC devices," said John Cornish, executive vice president of the System Design Division at ARM. "This technical innovation has unified CPU debugging with FPGA debugging to bolster user productivity. Altera and ARM have made this advanced tool technology with premium, productivity-boosting features widely available through Altera SoC development kits and the Altera SoC Embedded Design Suite. We believe this combination will deliver valuable benefits to our mutual customers."
The ARM DS-5 toolkit suite offers the most advanced multi-core debugger in the market for the ARM architecture. It supports debugging on systems running in asymmetric multi-processing (AMP) and symmetric multi-processing (SMP) system configurations. It is broadly used for board bring-up, driver development, OS porting, bare-metal and Linux application development, through JTAG and Ethernet debugging interfaces, and offers Linux and RTOS awareness.

ARM DS-5 Altera Edition toolkit features
 • Software debug view adapts to include the peripheral devices programmed by the developer into the FPGA fabric, providing a seamless view of both the hard and soft peripheral register memory map of the entire SoC.
 • The DS-5 Debugger simultaneously displays debug/trace data for the Cortex-A9 processor cores and CoreSight-compliant custom logic cores implemented in the FPGA fabric.
 • Altera USB Blaster JTAG debug cable supports both the DS-5 debugger and other Altera JTAG-based tools for the Altera SoC device.
 • Allows non-intrusive capture and visualisation of signal events in the FPGA fabric that can be time-correlated with software events and processor instruction trace.
 • Supports advanced, signal-level hardware cross-triggering between the CPU and FPGA logic domains, which enables cross-domain hardware/software co-debugging.
 • Includes the DS-5 Streamline performance analyser, which correlates software thread and event information with hardware counters from both the SoC and FPGA, enabling the identification and correction of system-level bottlenecks.

Pricing and Availability
The ARM DS-5 Altera Edition toolkit will be included in the Altera SoC Embedded Design Suite (Altera SoC EDS) Subscription Edition for $995.

More information about the Altera SoC EDS can be found at www.altera.com/soc-eds. More information about the ARM DS-5 Altera Edition toolkit can be found at www.altera.com/ds-5-ae. The Altera SoC EDS will start shipping in early 2013.




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