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Break differential-drive limits for an omnidirectional robot

15 Feb 2013  | Eileen Su, Yeong Che Fai, Tey Wei Kang

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Figure 6 shows the layout for processing input signals. Six D flip-flops are used, represented by the blocks labelled DFF. The first four D flip-flops prevent meta-stability in the QEI blocks. Meta-stability is a condition where output hovers between logic '0' and logic '1'. That can happen if the input changes too close to the clock edge that triggers the flip-flop. The four DFFs act as synchroniser that samples an asynchronous input, then produce an output that meets the setup and hold times as required in a synchronous system.

QEI block diagram

Figure 6: The QEI block diagram shows that the layout for processing input signals uses six D flip-flops (DFFs).


PWM block diagram

Figure 7: The PWM block diagram. The counter is compared to the value in PWM_1 to output a simple PWM pulse at the desired duty cycle.


To drive the motors, the PWM block is designed to interface the main controller with the H-bridge motor drivers as shown in figure 7. Upon receiving the triggered clock pulses from the clock pulses generator, the PWM_Counter is increased by 1. The counter is then compared to a constant value of 10,000. If it is greater than 10,000, then it will reset to zero. By doing this, a constant period of 0.2ms, which is equivalent to a 5kHz frequency, is achieved.

The counter is additionally compared to a variable named PWM_1. This is to determine the duty cycle of the generated PWM pulses. For example, if 50% of duty cycle is required, you can set the value of 5,000 into PWM_1. When the counter is less than PWM_1, the PWM output pin will be triggered 'ON.' In the case when counter value is greater than PWM_1, the pin will be triggered 'OFF.' Hence, a simple PWM pulse is generated.

Core formula in Labview

Figure 8: The core formula implemented in the Labview software.


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