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DCD unveiled tiny UART IP core

12 Mar 2013

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 Digital Core Design DuART

Digital Core Design has pushed out the door what it claims as one of the smallest UART IP cores in the market. The DμART implements separate BAUD clock line, false start bit detection, status report and internal diagnostic capabilities, detailed the company.

The DμART is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It can perform both, serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-serial conversion on data characters received from the CPU. The CPU itself can read the complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions, like overrun or framing.

The DμART includes also a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1) and producing a 16x clock, for driving the internal transmitter logic. Provisions are also included to use this 16x clock, to drive the receiver logic. It has been also equipped with a processor-interrupt system. As a result, the interrupts can be programmed according to the user's requirements, minimising the computing required to handle the communications link.

The DμART core is geared for applications, where the UART and MCU are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. DCD's solution is also suitable for a stand-alone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices as well, the company added.




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