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Equations, impact of setup and hold time

28 May 2013  | Deepak Kumar Behera, Karthik Rao C.G.

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Since Clock Insertion Delay is common to clock inputs for both flip-flops, it does not constrain the maximum operating frequency for the given setup. It can be seen that this circuit does not violate the hold constraint as given in equation (2).

Intuitively, we can look at equation (1) as follows:

(Time available for data to travel from FF1 to FF2) ≥ (Time needed for data to travel from FF1 to FF2)

Tclk + Tskew ≥ Tc2q + Tcomb + Ts2

Tclk + 0.25ns ≥ 0.1ns + 5ns + 3ns

Tclk ≥ 7.85ns

Thus a minimum Clock Period of 7.85 ns is required to prevent setup violation. This translates to a maximum operating frequency of 127.4MHz.

From the above example it is clear that to improve the maximum operating frequency, any of the following steps can be taken:

 • Decrease Tcomb between talking flops.
 • Increase Tskew if there is scope to do so.
 • Select flops with lower Tc2q and Tsetup.
Another way of looking at this is, reducing the operating frequency of the system helps mitigate setup violations, if any.


Impact of setup/hold constraints on clock to Q delay
Since latching circuit in a Flip-Flop is a back to back inverter (o/p of one inverter is i/p to the other inverter, as shown in figure 5), the I/O characteristic, as shown in figure 6, is derived from the characteristic of single inverter.

For the purpose of explanation, let's say 0V corresponds to logic LOW and 5V corresponds to logic HIGH. As seen from the adjacent diagram, if any value other than a perfect 0V or 5V is given as input to this back-to-back inverter, it will take some latching cycles to produce a stable inverted o/p. This delay accounts for the C2Q delay.

Figure 5: Back-to-back inverters for latching action.



Figure 6: IO characteristics.


If such delays accumulate over flops it may so happen that a data signal is missed by the clock edge at which it was supposed to be captured.


Reference
[1] Understanding the basics of setup and hold time


About the authors
Deepak Kumar Behera is a design engineer in Freescale Semiconductor, India Pvt. Ltd. with two years experience in power integrity, signal integrity and package analysis.

Karthik Rao C.G. is a design engineer in Freescale Semiconductor, India Pvt. Ltd. with two years experience in digital IP design.


To download the PDF version of this article, click here.


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