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Understanding DO-254 requirements traceability

10 Jun 2013  | Louie De Luna

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Taking a closer look into the details of the RTCA/DO-254 guidance in conjunction with the FAA Order 8110.105, traceability in the context of FPGAs entails linking the CCA requirements to the FPGA requirements, and linking FPGA requirements to the design and verification data and results. Proving that this level of traceability exists to the certification authority helps ensure that all design and verification activities for the FPGA under test are requirements-based.


Responsibilities of the applicants
In working through the different stages of the FPGA design life cycle, the responsibilities of the applicants to meet the objectives for traceability are as follows:


Requirements capture
 • Link each FPGA requirement to the related CCA requirement it covers.
 • Generate a downstream traceability report and ensure every CCA function has been allocated to the FPGA and captured as an FPGA requirement.
 • Generate an upstream traceability report and ensure that each FPGA requirement traces up to the appropriate CCA requirement. Each FPGA requirement that does not trace up to a CCA requirement may be considered as a derived requirement and must go through the validation process.
 • Baseline or record the trace data between CCA requirements and FPGA requirements.


Conceptual design
 • Link each conceptual design data to the related FPGA requirement it covers.
 • Generate a downstream traceability report to ensure that each FPGA requirement is covered by a conceptual design data.
 • Generate an upstream traceability to expose unnecessary conceptual design data.
 • Baseline or record the trace data between FPGA requirements and conceptual design data.


Detailed design and implementation
 • Link the specific lines of the HDL design source (single line or multiple lines of code) to the related FPGA requirement it covers.
 • Generate a downstream traceability to ensure that each FPGA requirement is fully implemented by an HDL function. FPGA designers must create additional functions as needed to fully implement each FPGA requirement.
 • Generate an upstream traceability to expose unused HDL design functions. Unused functions of the HDL code may lead to unexpected behaviour of the device, and must be removed or updated.
 • Ensure that the post-synthesis and post-layout design meet the specified constraints.
 • Baseline or record the trace data between FPGA requirements and HDL design data.


Verification
 • Link each verification test scenario to the related FPGA requirement it covers. Test scenarios are created based on the FPGA requirements, and they are reviewed for suitability and completeness to cover the related FPGA requirement. Test scenarios define how each FPGA requirement will be verified, and includes the appropriate input conditions, test sequence and expected results.
 • Generate a downstream traceability to ensure each FPGA requirement is covered by a test scenario.
 • Generate an upstream traceability to expose unnecessary test scenarios.
 • Baseline or record the trace data between FPGA requirements and test scenarios.
 • Link the specific lines of the testbench (single line or multiple lines of code) to the related test scenario it covers.
 • Generate a downstream traceability to ensure that each test scenario is fully implemented by the testbench. Verification engineers must create the testbench with the appropriate test inputs, sequence and expected results as defined in the test scenarios.
 • Generate an upstream traceability to expose unused functions or code of the testbench that needs to be removed or updated.
 • Baseline or record the trace data between test scenarios and testbench.
 • Link the specific simulation results to the related test scenario it covers. Simulation results are a combination of simulation logs, waveforms and coverage data. These results are analysed and reviewed for correctness.


Figure 2: Spec-TRACER downstream traceability.


Benefits of requirements traceability
Implementing and maintaining traceability throughout the FPGA development cycle ensures that what is being designed and tested is based on the requirements. Establishing traceability promotes better project management, and provides an efficient way to organise, connect and track the FPGA development cycle. Although not explicitly defined in the guidance, requirements traceability offers significant benefits to the organisation when done correctly. Several examples of the benefits are described below.


Exposure of coverage gaps
During the FPGA requirements capture process, running a downstream traceability from CCA to FPGA requirements exposes CCA requirements that are not covered by FPGA requirements. As an example shown in figure 2, both CCA-002 and CCA-007 are not covered by any FPGA requirement. This is a result of either: the related FPGA requirements are not correctly linked to CCA-002 and CCA-007 requirements, or that the CCA-002 and CCA-007 requirements are not properly allocated to the FPGA. Either way, proper measures must be taken to correct this coverage gap.

Likewise, during the rest of the FPGA design life cycle, running downstream traceability exposes FPGA requirements that have not been implemented by an HDL function, FPGA requirements that have not been covered by a test scenario, and test scenarios that have not been implemented by a testbench.

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