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Mentor Graphics rolls verification IP for MIPI interfaces

25 Jun 2013

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Mentor Graphics recently unveiled its MIPI-protocol verification IP (VIP) for use with their latest-generation Veloce hardware emulation platform. The VIP allows engineers to exhaustively stress test a device under test (DUT) that includes one or more MIPI protocol interfaces on their SoC, and run verification cycles at orders of magnitude faster than simulation.

The MIPI VIP enables the use of stimuli generated by modern simulation test benches, including SystemVerilog/UVM, and SystemC-based environments, and applies them to a MIPI based, design-under-test running in the Veloce emulator. Since the connection between the test bench and the VIP is at a transaction-level rather than signal interface, a high level of performance is delivered.

The new VIP supports users of the MIPI camera and display-based protocols, CSI and DSI, and is compatible with the Questa functional verification platform as well as the Veloce hardware emulation platform.

Emulation-ready VIP is used as a part of the strategy for verifying SoCs containing multiple protocol interfaces on chip. Users can develop test benches in one of several supported high-level verification (HVL) environments, and then seamlessly interchange between RTL verification and acceleration. This delivers an effective and productive environment to develop new, leading-edge SoCs and accelerate delivery schedules.

The Veloce2 emulator is a high-performance, dual-mode accelerator/emulator, delivering twice the performance and capacity of previous generations for both transaction-based verification and traditional in-circuit emulation (ICE). With an extensive portfolio of vertical market solutions, the Veloce2 emulator is the platform of choice for networking, wireless, multimedia, storage, and embedded systems applications.




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