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Synopsys shows M-PCIe IP interoperability

27 Jun 2013

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Synopsys Inc. has revealed what it boasts as the industry's first M-PCIe (mobile PCI express) interoperability demonstration between M-PCIe interfaces from Synopsys and Intel using M-PCIe-based switch and end-point devices. M-PCIe is an engineering change notice (ECN) to the PCIe specification and allows designers to leverage their existing knowledge and software investments in PCIe to cut power consumption of SoCs for low-power applications. Synopsys' M-PCIe solution, which includes silicon-proven DesignWare MIPI M-PHY technology and M-PCIe Controller IP, provides early support for the recently announced M-PCIe specification, enabling designers to speed up development of M-PCIe-based designs to hit critical market windows, the company stated.

The M-PCIe ECN to the PCI Express specification supports the low-power MIPI M-PHY by modifying the definition of the PCIe controller's physical layer. Synopsys has implemented this enhancement to its PCI Express controller IP, which has been used in over 750 designs, to work with its silicon-proven M-PHY and provide designers with a low-risk M-PCIe solution. Synopsys' implementation of the M-PCIe ECN includes the power saving features of the PCIe specification and adds support for asymmetric link widths and improved latency. The asymmetric links defined in the M-PCIe specification allow designers to provision different bandwidths in upstream and downstream directions for increased design flexibility and effective power allocation. The M-PCIe ECN also takes advantage of the M-PHY's specification for improved entry and exit latencies when going into and out of low-power modes, saving critical power for battery-powered devices.

DesignWare Controller IP
The DesignWare Controller IP for M-PCIe is based on Synopsys' silicon-proven PCI Express controller IP, which has been extensively validated with multiple hardware platforms, PHYs and PCIe verification suites. Existing features and functions, such as application interfaces, embedded DMA engines, ARM AMBA AHB/AXI bridges, support for multiple lanes (x1 to x16), and support for multiple data path widths, are proven in silicon and in wide customer use. In addition, DesignWare Controller IP for M-PCIe includes selectable PHY technology, which allows one controller to support both PCI Express with a PIPE-interfaced PCI Express PHY and an RMMI interface for connection to Synopsys or third-party M-PHY. Because the DesignWare Controller IP for M-PCIeis based on the proven Synopsys PCI Express Controller IP, existing designs can be easily migrated into M-PCIe designs, while new designs benefit from the silicon-proven features.

Synopsys' M-PCIe solution incorporates the silicon-proven, High-Speed Gear3 DesignWare MIPI M-PHY. Designers can take advantage of the DesignWare MIPI M-PHY's support for the latest M-PHY specification (Version 3.00), Type-1, multiple gears (1,2,3), and multiple rates (A,B) to further reduce system power consumption for M-PCIe designs. Using a variety of high-speed and low-speed burst modes with power management modes, including stall, sleep and hibernate with quick entry and exit capabilities, Synopsys' DesignWare MIPI M-PHY IP achieves required data rates while meeting the stringent power and area requirements of low-power devices, stated Synopsys.




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