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Soft IP Core compatible with 8051, 80390 instruction sets

02 Aug 2013

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Digital Core Design has unveiled a soft IP Core that is 100% binary compatible with 8051 and 80390 instruction sets. The DP80390 features a pipelined RISC architecture that executes up to 200 million instructions per second and consumes just 8120 gates. Also, the DP80390 is a technology independent IP Core, so it can be easily implemented in both ASIC and FPGA, added the firm.

The DP80390 is a high performance, speed optimised soft core of a single-chip 8bit embedded controller intended to operate with fast (typically on-chip) and slow (off-chip) memories. It supports up to 8MB of linear code space and 16MB of linear data space.

The pipelined RISC architecture of the DP80390 executes 85-200 million instructions per second, running the Dhrystone 2.1 benchmark from 11.46 to 15.55 times faster than the original 80C51 at the same frequency.

The DP80390 is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow. Each of DCD's 80390 Cores has built in support for the DCD's Hardware Debug System, called DoCDT. It is a real-time hardware debugger, which provides debugging capability of a whole SoC. And unlike other on-chip debuggers, the DoCD provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals.

The CPU features up to 14.632 VAX MIPS at 100MHz, up to 256B of internal (on-chip) data memory, up to 8MB of linear Program Memory, 64kB of internal (on-chip) program memory, 8MB external (off-chip) program memory and up to 16MB of external (off-chip) data memory. Additionally, the device offers an interface for additional special function registers, static synchronous design, positive edge clocking and no internal tri-states and are scan test ready.




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