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Semtech unit to launch SiIP PHY to support CEI 25G and 28G

06 Sep 2013

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Semtech's Snowbush IP group is set to launch the SBMULTC2T28HPM28G Silicon Intellectual Property (SiIP) platform for next-generation, high data-rate chip-to-chip and chip-to-module products used in Petabyte storage, Terabit networking and Exascale computing. The new SiIP PHY can be programmed to support multiple Common Electrical Interface (CEI) standards ranging from 25 to 28 Gigabits per second (Gbps).

The area, power and latency of the Snowbush SiIP PHY have been optimised to minimise the impact when used in an SOC, ASIC or ASSP. A post-silicon tuning capability allows customers to adapt the performance of the PHY to different operating environments.

The new platform represents the eighth generation of a programmable analogue front end that Semtech-Snowbush IP pioneered for handling many standards from a single silicon macro. The architecture was initially developed at 65nm and was ported to 40nm. At 28nm, the architecture has seen three generations of silicon and is shipping in production.

The SBMULTC2T28HPM28G has an analogue front end (AFE) that includes the transmit (Tx) and receive (Rx) path circuitry along with auxiliary blocks for clock generation, test and biasing. The Tx driver is a highly programmable block including multiple registers to allow adjustment of TX amplitude, de-emphasis and pre-emphasis.

The Rx path is also highly programmable to meet the requirements of many serial I/O applications. Advanced equalisation compensation reacts to the actual channel characteristics and extracts clean data that is provided to the on-chip parallel interface. Firmware supports the calibration and adaptation in both the Rx and Tx data paths. Implemented through a digital control interface, the software provides a flexible means of adjusting performance to meet different channel characteristics.

The Rx architecture includes a multi-stage continuous time linear equaliser (CTLE), passive linear equaliser (PLE) and variable gain amplifier (VGA). The receive path also includes a decision feedback equaliser (DFE) for crosstalk suppression and extended reach. All stages feature digital offset calibration and adaptive equalisation to handle a range of channel conditions. The Rx architecture supports both AC and DC coupling.

The RX also includes a high bandwidth data clocked CDR to achieve high jitter tolerance. The CDR relies on a digital architecture and includes a sampling phase adjustment capability.

The receiver includes a non-destructive on-chip eye monitor to allow the user to "see" the eye opening at the receive slicer after the application of both transmitter and receiver equalisation. This capability can be used to help adjust the transmitter and receiver equalisers and characterise link margin.

The TX architecture includes a source series terminated (SST) transmit driver with a feed forward equaliser (FFE). The FFE has per-cursor and post-cursor taps with both manual and adaptive control.

The TX clock generation is based on a fractional-N LC-PLL for superior jitter performance. An advanced, digitally assisted calibration approach is supported by firmware (same as Rx). Digitally controlled calibrations include TX termination, TX PLL frequency, TX PLL amplitude, TX phase alignment and DCD. Optional digital control supports link training.

The SBMULTC2T28HPM28G includes a minimal latency on-chip digital interface. Multiple parallel interface widths are supported and the digital interface is designed to inter-operate with industry available PCS and MAC (link) layer logic.

The Silicon IP PHY will ship in October (as GDS). System-level models are available today under NDA for performance testing and integration.




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