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SoC internal channel characterisation with ADC

26 Sep 2013  | Kushal Kamal, Siddi Jai Prakash

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Now let us try to analyse the voltage profile of the ADC driver in two cases: when the ADC driver has large current driving capacity (strong driver) and a case when it does not have a large current driving capacity (weak driver). At the beginning of the sampling phase, as soon as the sampling switch closes, the sampling capacitor load is seen by the ADC driver. There will be a large inrush current at that moment because of the capacitive charging action.


Figure 3: Strong and weak driver Voltage profile during sampling and conversion time.


This instantaneous current surge might result in a drop in the voltage level of the ADC driver. As charge (current x time) is accumulated on the ADC capacitor, the current requirement by the sampling capacitor would reduce and the voltage would come back to its original level .

The time taken by the voltage to come back would depend on the current that the driver can support. If the driver is strong and it can supply large amount of current then it would eventually deposit more charge on the capacitor in lesser time and bring the potential of the sampling capacitor close to that of the ADC driver. This is seen in the waveform for the strong driver.

But when we talk about a weak driver then the current might be low and the total charge deposited on the sampling capacitor in the sampling time might be less and would eventually mean that the potential sampled at the sampling capacitor is not correct. This can be seen in the behaviour of the weak driver profile. It would essentially mean that with a weak driver at the ADC channel the voltage sampled may be less and thus inaccurate results may be sampled by the ADC.


Overcoming strong and weak driver voltage profiles
To overcome this issue the sampling time of the ADC must be increased. This can be achieved in two ways. Either increase the clock pulses in the sampling time or decrease the frequency of operation of the ADC. Many ADC architectures might not support a feature of multiple sampling times so we may need to work with low frequency when trying to convert the analogue voltage of a weak driver.

This behaviour can be seen in the next diagram. In this diagram we see that the sampling time of the ADC was increased by increasing the number of clock cycles to three clock cycles. Since now the ADC Driver gets almost 50% more time to accumulate the charge, even with a lower current the ADC could sample the correct amount of charge and the ADC output now would be fine.


Figure 4: How the voltage sampled at the sampling capacitor can be corrected when supplying the ADC with a weak driver.


In many SoCs it is a customer need to sample multiple signals that are internal to the SoC. Also during characterisation of IPs even the designers and SoC engineers use the ADC and convert many of the IP signals that are internal to the SoC via the ADC and get crucial information about the working of the IP. It's not only the external channels and source that the ADC samples now, it even samples multiple internal channels.

In many of the internal channels the issue of weak drivers might come. It might also happen because these signals are driven on to the ADC channel via a transmission gate which might have a varying large resistance depending on what the potential of the signal is being exposed. Since these channels are generally driven by small buffers, they are not capable of effectively supplying a load as big as the sampling capacitor of the ADC. Therefore, it is supremely important to either increase the sampling time during conversion of such channels or make the frequency low in order to capture correct behaviour of the IP from the ADC.

Therefore verification/validation/test engineers who use an ADC to characterise internal IPs like a DAC or PMC internal signals like a band-gap, the reference or various other thresholds must take care of the sampling time need and strong/weak driver profile.


About the authors
Kushal Kamal and Siddi Jai Prakash are with Freescale Semiconductor.


To download the PDF version of this article, click here.


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