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TSMC updates 16nm FinFET, 3D IC reference flow

24 Sep 2013

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EDA firms Cadence Design Systems and Mentor Graphics have separately announced that their digital tool sets have been updated to enable customers to tap the benefits of TSMC's 16nm FinFET process such as higher performance, lower power consumption and smaller area. The TSMC 16nm Custom Design Reference Flow development is built on top of the ongoing 16nm FinFET tool certification, which is currently at V0.5 of Design Rule Manual (DRM) and SPICE, heading towards V1.0.

Cadence's digital design tools were applied in a 16nm FinFET quad-core design that incorporated an ARM Cortex-A15 mobile processor for the validation of methodologies in TSMC's 16nm reference flow. The flow was implemented with the Cadence Encounter Digital Implementation System and includes Physical Verification System, QRC Extraction, Tempus Timing Signoff Solution and Encounter Power System tools.

Mentor's Olympus-SoC place and route system has been enhanced to meet the TSMC 16nm design enablement and certification requirements in support of FinFET designs such as pattern density-aware floor planning for early metal fill density checks, MiM capacitor insertion for IR drop improvement, and support for high-resistance layer routing/optimisation enabling better quality of results. In addition, the Calibre InRoute product allows Olympus-SoC customers to natively invoke Calibre DRC/DFM/DP signoff engines during design for more efficient and faster manufacturing closure.

TSMC also collaborated with Cadence for a new reference flow that enhances chip-on-wafer-on-substrate (CoWoS) chip design and certified using a memory-on-logic design with a 3D stack. Meanwhile, its partnership with Mentor expands support for interposer- and TSV-based physical design, verification, extraction, thermal and testing to full 3D.




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