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Memoir launches multi-port memory generators suite

24 Oct 2013

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Memoir Systems has rolled out Renaissance for Datacom, a suite of multi-port memory generators that allows SoC developers to maximise their multi-terabit networking solutions. It enables them to create performance memory solutions for packet buffers, Netflow, policing and state tables, statistics counters, and multi-port FIFOs, among others. The product combines the company's memory IP-generating pattern-aware technology with better performance, and lower area and power. It has potential applications in datacenters, switches and routers, software defined networks (SDN), and cloud infrastructure.

"There are fundamental limitations with existing silicon technology that need to be overcome to enable terabit networking. As we crank up switching bandwidths into the terabit domain, the power consumption and heat generation alone make these solutions problematic for large scale data centres," said Martin Izzard, former R&D VP at TI who is now CEO at a stealth mode start-up. "Terabit era networks will require new innovative technologies such as Memoir's Renaissance for Datacom that not only enable higher bandwidths, but also are much more energy-efficient."

Renaissance for Datacom is based on Memoir's Renaissance 2X, 4X, and 10X families of embedded memories (based on Memoir's award-winning Algorithmic Memory), which offer deterministic, fully random access memory performance up to 10X memory operations per second (MOPS). Although many applications require deterministic memory performance, some only access memory in a specific pattern. Renaissance for Datacom recognises four common memory patterns: allocation access used in packet buffers, read modify write access used to update memory in Netflow, policing and state tables, read add modify access used to maintain statistics counters, and sequential access used in multi-port FIFOs. The product includes four unique memory cores – Allocation, Update, Counter, and Sequential memory core tailored for the above functions. These represent patterns that are commonly used, independent of the implementation, in a wide set of applications in the datacom SoCs.

Pattern-aware technology enables Renaissance for Datacom to extend memory performance all the way up to 16X MOPS for datacom SoCs. For instance, using an 8R8W allocation memory, developers can build a fully deterministic shared memory buffer with multi-terabit bandwidth in 28nm process. Another key benefit of pattern-aware technology is its ability to reduce area, power, and energy consumption. With a typical high-performance SoC burning 80-100W, lowering the power and energy envelope is critical. Pattern-aware technology reflects a deeper understanding of the memory access patterns that in turn enables more intelligent management of memory. It enables fine-grained power control of physical memory and reduces memory energy consumption by up to 70 per cent, translating to up to 5 per cent lower energy consumption on end systems.

Renaissance for Datacom offers deterministic memory performance, activity aware power control, and runtime error detection and correction. It also offers physical design aware RTL and that is formally verified, with no further silicon verification required. The memories use simple SRAM like interfaces, and integrate into a normal SoC design flow. Since the memories are RTL based, they are compatible with any process, node, or foundry.




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