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Aldech rolls out Active-HDL version 9.3 FPGA design tool

25 Oct 2013

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Aldech has debuted version 9.3 Active-HDL FPGA designer tool. The tool boasts a user-defined directory structure, allowing engineers to create project structures compatible with standard Synthesis and Place & Route tools. The tools, in turn, allow one common project structure to be used between multiple vendor tools.

The tool's Multi-design projects involve many settings, such as setting a working directory, updating local variables, setting a script mode, executing specific macros, etc. Active-HDL 9.3 introduces a load-time setup file approach that automatically loads these settings.

After initial set-up, the simulator can be set at different running mode with single click. This feature allows users to run Active-HDL in the right mode for each task; Optimised mode will run simulator at the highest possible speed while Debug and Coverage mode will run at reduced speed while collecting data for later analysis.




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