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Reflex CES unveils 64B/66B IP core based on Altera FPGAs

30 Oct 2013

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Reflex CES rolled out a 64B/66B IP core that can be used to link up Xilinx and Altera high speed transceiver FPGAs at a speed of 14.1Gbit/s. The Aurora-like IP cores come with reference designs, encrypted test-benches and encrypted or VHDL source code licence agreements.

Based on Altera FPGAs, the new IP core supports 64B/66B encoding and high-speed interfaces up to 14.4Gbit/s, enabling interoperability between Xilinx and Altera FGPAs, with an effective bandwidth of up to 97%.

Targeted specifically at complex, embedded military and telecommunications, networking applications, the 64B/66B FPGA IP core allows designers to choose the most appropriate FPGA solutions to meet their needs, from single or multiple vendors. The new IP core offers a fully compliant implementation of the Xilinx Aurora 64B/66bB scalable, link-layer protocol for high-speed serial communication, and allows for communication between FPGAs through a backplane. Based on this open standard protocol used to transport data with higher connectivity performance for chip-to-chip and board-to-board architecture, the Reflex CES Aurora-like 64B/66B IP core allows designers to move data from point-to-point across 1 to 16 serial lanes at up to 14.1Gbit/s.

The core features user flow control, native flow control, immediate and completion mode, as well as modules to convert interfaces to and from streaming Advanced eXtensible Interfaces (AXI). This low protocol overhead IP core offers customers minimal data rate transfer latency with minimal logic resources (900 equivalent logic cells for a 4 lane configuration in simplex mode) for cost effective implementation.

The Reflex CES Aurora-like 8B/10B and Aurora-like 64B/66B IP Cores are available with encrypted or VHDL source code licence agreements, encrypted test-benches, reference designs and a user guide.




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