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Dual DC/DC controller for DDR power

11 Nov 2013  | Ding Li

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The LTC3876 is a DDR power solution, compatible with DDR1, DDR2, DDR3, and DDR4 lower voltage standards. The IC includes VDDQ and VTT DC/ DC controllers and a precision linear VTT reference. A differential output sense amplifier and precision internal reference combine to offer an accurate VDDQ supply. The VTT controller tracks the precision VTTR linear reference with less than 20mV total error. The precision VTTR reference maintains 1.2% regulation accuracy, tracking one-half VDDQ over temperature for a ±50mA reference load.

The LTC3876 features controlled on-time, valley current mode control, allowing it to accept a wide 4.5V to 38V input range, while supporting VDDQ outputs from 1.0V to 2.5V, and VTT and VTTR outputs from 0.5V to 1.25V. Its phase-locked loop (PLL) can be synchronised to an external clock between 200kHz and 2MHz. It also features voltage-tracking soft-start, PGOOD, and fault protection.



Figure 1 shows a DDR3 power supply that operates from a 4.5V to 14V input. Figure 2 shows efficiency curves for discontinuous and forced continuous modes of operation.


Load-release transient detection
As output voltages drop, a major challenge for switching regulators is to limit the overshoot in VOUT during a load-release transient. The LTC3876 uses the DTR pin to monitor the first derivative of the ITH voltage to detect load release transients. Figure 3 shows how this pin is used for transient detection.

The two RITH resistors establish a voltage divider from INTVCC to SGND, and bias the DC voltage on the DTR pin (at steady-state load or ITH voltage) slightly above half of INTVCC. For a given CITH1, this divider does not change compensation performance as long as RITH1/ RITH2 equals RITH that would normally be used in conventional single-resistor OPTI-LOOP compensation.


The divider sets the RC time constant needed for the DTR duration. The DTR sensitivity can be adjusted by the DC bias voltage difference between DTR and half INTVCC. This difference could be set as low as 100mV, as long as the ITH ripple voltage with DC load current does not trigger the DTR. If the load transient is fast enough that the DTR voltage drops below half of INTVCC, a load release event is detected. The bottom gate (BG) is turned off, so that the inductor current flows through the body diode in the bottom MOSFET.



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