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IP's role in new generation data centre SoCs

11 Dec 2013  | Ron DiGiuseppe

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The ONF members consist of major carrier and data centre operators including Facebook, Google, Microsoft, Verizon, and Amazon, as well as system suppliers to those operators such as Cisco, Dell, Fujitsu, and HP. The participation of major semiconductor ASSP suppliers including Broadcom, Freescale, LSI, Marvell, TI, Netronome, and others within ONF are creating a new class of SoCs for data centre applications.

The transition to SDN can be seen in a number of new ASSPs in development or recently introduced which support SDN Openflow such as multi-port Ethernet switch ASSPs with Openflow optimised switch fabrics or communication processors that run OpenFlow SW stacks including autonomous OpenFlow accelerators. The new hybrid communication processors performing data plane classification, packet processing, traffic management and security processing are being enhanced to support SDN and OpenFlow.


Figure 2: Reducing data centre power with micro servers.


Typical IP requirements for advanced communication processors include high data rate memory interfaces such as DDR4 and a large combination of I/O interfaces such as PCI Express 3.0, and 10G – 40G Ethernet ports to connect the chips to the network fabric. The introduction of new communication processors into the market is an exciting architectural transition in the data centre network.

On the compute side, these architectural trends are resulting in micro servers that incorporate a new class of processor SoCs designed to reduce power dissipation. The micro server architecture is composed of multiple workload-focused server nodes in a shared chasis, which is intended to reduce data centre power, cost, and space. Micro servers are designed for modest data centre workloads such as web servers, offline analytics, web content delivery, and memcache.

Obviously, any approach to reduce power in compute servers will benefit mega data centres and the semiconductor industry is responding to this need by creating lower power host processors for micro servers. Reducing power for micro server host processors starts with selecting a low-power processor such as Intel's recently released 2nd generation 64bit Atom core. This core is used in Intel's C2000 processor family which is well-suited to the needs lightweight scale-out workloads, such as dedicated hosting and static web serving. A number of leading semiconductor suppliers have chosen ARM's 64bit v8 processor core for their next-generation SoCs for low-power micro server applications.

Further power reduction can be achieved at the system level by integrating various functions that have traditionally been implemented as individual chips on the motherboard, into the processor ASSP. Integrating processor cores, interface protocols, and a high-performance memory sub-system into a heterogeneous architecture consisting of various protocol accelerators provide the full functionality of a server on a single SoC.


Communications processors for SDN applications
When we look at these two new classes of SoCs: communications processors for SDN applications and low-power processors for micro servers, it is important to define the design criteria from the network and compute systems perspective to ensure the ASSP implementations are efficient. Designers building SoCs for these applications need a combination of high-performance and power-efficient IP functions to help deliver total system throughput and meet the quality-of-service requirements. System and semiconductor SoC designers and architects need to consider multiple related design goals when defining SoCs for next-generation data centres.

One essential criterion is low latency to meet multimedia IP traffic class of service guarantees. With data centre virtualisation driving application workloads—data centre SoCs must minimise latency. In addition to low latency, the SoCs need to minimise power dissipation while adopting the latest advanced protocols and key features that data centre applications require. Another key challenge for data centre SoCs is ensuring continuous operation, so the chips need to implement key reliability, availability, and serviceability (RAS) techniques to minimise downtime in the data centre switches and servers.

Targeting the latest foundry design nodes is also important because next-generation data centre SoCs will use the latest 16/14-nm FinFET design processes currently being adopted by the semiconductor industry. Addressing the SoC challenges for low latency, low power, advanced protocols, RAS, and availability of mission critical IP for 16/14-nm FinFET are key issues for next-generation SoCs for data centre applications.

A common set of IP is required for most SDN switching, communication processors, and server host processor SoCs. The IP functions include next-generation DDR4 SDRAMs, PCIe Express 3.0, 1G through 40G Ethernet, logic libraries and embedded memories to implement L1-L3 cache. When implementing these mission critical IP, it is important to ensure each IP meets the key criteria of low latency, low power, advance protocols, RAS and 16/14-nm FinFET availability. A closer look at each protocol highlights the important features which IP providers must provide to meet data centre design criteria.

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