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IP's role in new generation data centre SoCs

11 Dec 2013  | Ron DiGiuseppe

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Constructing a complex SoC with multiple IP functions requires a comprehensive solution for the full protocol stack of each individual IP block. In addition to the protocol's data link controller, a silicon-proven Physical Layer (PHY) designed for the specific foundry design process needs to work closely with the controller layer. Functions like DDR4, PCIe 3.0, 1G/10G/40G Ethernet, SATA 6G and USB 3.0 must all contain PHYs that are characterized for 16/14-nm FinFET design processes. The PHY's data and control interfaces should also operate smoothly with the data link controller. A comprehensive, proven IP portfolio with application specific features such as Synopsys DesignWare IP4 is critical to implement a complex SoC for SDN optimised switches and low-power micro servers. The portfolio and system-level design solutions must be optimised for high-performance, low power and low latency, and support advanced process technologies from 28 nm to16/14-nm FinFET. To accelerate the SoC design completion, a suite of Verification IP matching the implementation IP is also needed.


Figure 3: Data centre SoC for SDN communication processors and micro servers.


Designing the SoC
Designing the SoC with all these functional blocks and protocols into a heterogeneous system can be complex, especially if you have to balance the SoC resources among the application processor, application sub-systems, I/O, memory management, and protocol acceleration engines, which differentiate many data centre SoCs. Data Centre SoCs are differentiated by the mix of processors, I/O, memory, and processor offload/acceleration engines such as security/encryption offload, OpenFlow acceleration, Hadoop acceleration, and workload balancing.

It is critical to define the correct hardware/software partitioning when architecting the SoC. Accurate System-C-based Transaction-Level Models (TLM) representing the SoC building block allow system architects to build a virtual design and simulate the SoC performance for various workloads and design trade-offs. Close correlation of the loosely timed System-C TLM models for the IP building blocks and processor IP allows architecture trade-off decisions based on accurate performance rather than best guess. System-C development environments such as Synopsys Platform Architect is tuned for cache coherent interconnect and contain ARM 64bit v8 CPU models. In addition, TLM models of the IP enable the concurrent design to perform system simulations for hardware/software architecture planning. The full system environment within Platform Architect also enables early software and firmware development well before SoC prototyping or engineering samples arrive, accelerating the SoC development by up to 12 months.

Exciting times are ahead for the next-generation of data centre applications including network switches and compute servers. As ASSP suppliers implement a new class of SoCs supporting the latest SDN architectures and low-power micro servers, they will rely on proven third-party IP to help them quickly integrate the required functionality and get their products to market fast. While doing so, they should keep in mind the five key IP needs to address data centre requirements: reducing latency, reducing power, supporting advanced protocols, meeting RAS requirements and providing a strong FinFET process technology roadmap.


References
1. Cisco Visual Networking Index 2013

2. Cisco Global Cloud Index 2013

3. The Data Centrer Journal, Aug 2013

4. Synopsys' DesignWare IP portfolio for data center SoCs


About the author
Ron DiGiuseppe is the Senior Strategic Marketing Manager in the Solutions Group at Synopsys.


To download the PDF version of this article, click here.


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