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Configuration for power systems based on PMBus 1.3

19 Mar 2014  | Michael Jones

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Do you find yourself working with a PMBus-based power system for a product that uses FPGAs, ASSPs, or ASICs? Or maybe you need to design from scratch a power management controller for your product, and you are evaluating various ways of implementing it. The examples that follow may give you a starting point for the system design and compare some consequences of the different choices.


Terminology and background on AVS
The PMBus Rev. 1.3 specification, which is being drafted now and should be released by the end of March 2014, incorporates significant changes intended to enhance the effective bandwidth of the bus for usage in controlling multiple power supplies in a system (see references at the end). This allows very capable and extensible implementations of system power controllers based on the physical layer definition and command set of the new specification.

For the purposes of this article, we will refer to circuits or sub-systems used for the purpose of controlling, coordinating, and monitoring multiple power supplies as a "power management controller (PMC)" to distinguish these functions from the more traditional "PWM power controller ICs" (which may regulate one or more voltage rails), and from "system management controllers (SMCs)" which may also deal with other functions such as fans, interlocks, displays, boot management, etc. A PMC defined in this way may be implemented with one or more ICs, and may be on the same or a different printed circuit assembly (PCA) as the power supplies it controls.

With the new PMBus 1.3 specification, a significant new function is available to enhance the control of power for high-density logic devices such as System on a Chip (SoC) Processors, Field Programmable Gate Arrays (FPGAs), Application Specific Standard Products (ASSPs), and Application Specific Integrated Circuits (ASICs). This new function is a dedicated high-speed bus (5-50MHz) which allows immediate control of one or more regulated voltages to the logic device for a technique called Adaptive Voltage Scaling (AVS). This three-wire bus is similar to the SPI bus, and will be referred to as the AVSBus. PMBus 1.3, with its speed improvements and the new AVSBus, are known as PMBus+.

As the logic devices progress to smaller semiconductor process nodes along with recent leading-edge microprocessors, it follows that the power control requirements will become similar to those that have been used for microprocessors for several years, including AVS. An effective implementation of AVS for these devices can result in a very significant reduction in power consumption for many speed grades of the logic devices and can enable unprecedented integration of power control and monitoring with these devices.

With the introduction of the new AVSBus, there are new architectural questions and considerations which should be dealt with in the design of the power controller system. The rest of this article addresses some of these considerations. We will refer to the high-density logic devices as FPGAs, but similar arguments can be made for the other types of logic devices.


Example power controller architectures
The AVSBus defined in the Rev. 1.3 PMBus specification establishes a high-speed power control bus between the logic device (the load and AVSBus master) and its power regulator (the power source and AVSBus slave). This raises new questions on the bus topology for a PMC. Can the new bus connect to the PMC? Does the PMBus need to connect to the logic device (the load)? Below are shown several possible bus implementation topologies, along with discussion of advantages and disadvantages for each case.


Case 1: Simple PMBus
Here (see figure below) is an example system configuration with a PMC which happens to be on the same PCA as the logic chips. As the diagram shows, there are multiple Point of Load (POL) voltage regulators for the FPGA chip, as well as possibly other chips. These can all be controlled by a single PMC for proper voltage sequencing in the system and a single point for monitoring any faults in the power system. The Rev. 1.3 specification has several new additions to improve the speed and performance of the bus in this configuration.




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