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Configuration for power systems based on PMBus 1.3

19 Mar 2014  | Michael Jones

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In this implementation, it makes sense for the PMC to be the PMBus master and each of the voltage regulators to be PMBus slave devices. This would be the traditional implementation of PMBus Rev. 1.2, before the introduction of AVSBus.

There may be some communications desired from the logic device to the PMC, as shown with the blue line labelled "Serial Control," for the purpose of telling the PMC the correct power control parameters for the logic device. This bus could take many forms, typically SMBus, I2C, SPI, or another PMBus. The diagram shows the PMC to be the "Serial Control" bus master and the logic device being powered as the bus slave device. This seems to be the preferred implementation, since it requires only the simpler bus slave logic implementation in the FPGA. The FPGA also does not need to store and produce the codes for all of the various bus commands. Both these factors maximise the fraction of the logic device which can be dedicated to customer data processing functions, as opposed to power control infrastructure.

Another variation on this bus topology could be to connect the PMBus to the "Serial Control" bus on the target FPGA. We will deal with this more in a later diagram. The FPGA could simply occupy another slave address on the PMBus.

The bus labelled "Other Control" could also take many forms, such as Enable lines, Chip Select lines, or tracking command voltages to control sequencing, or it may be omitted altogether if the commands of the PMBus are fully utilised.


Case 2: PMBus with AVSBus
In the next case, the PMC controls other items beyond the power system (such as the two fans shown), so it is labelled as a System Management Controller (SMC). In this diagram (below), it is located on a separate PCA.




Notice the addition of the AVSBus on two voltage rails of the FPGA in this example. This diagram shows the AVSBus usage as intended by the PMBus Rev. 1.3 specification. But now several questions arise. Should the AVSBuses connect to the SMC (for PMC functions)? How do the POLs receive the on/off and voltage commands to implement AVS – do they come from the PMBus or AVSBus? Can the AVSBuses for two POLs be joined and controlled by only one master? What if one of the voltage rails is produced by multiple parallel regulators?

The Rev. 1.3 specification assumes that the POL is at least a PMBus slave and an AVSBus slave. Thus, the PMC can use the PMBus to configure and enable the POLs and monitor them for faults in the usual ways over PMBus. The Rev. 1.3 specification allows the voltage control to be initiated by PMBus as an initial value (the "Boot Value"), and then be handed over to AVSBus control for fast updates by the load device (which is the AVSBus master).

Since the AVSBus is a high-speed bus, the bus and circuit board engineering would become more complicated for signal integrity if it needed to connect to the SMC/PMC (especially if the SMC/PMC function is on a separate board, as shown). Fortunately, the AVSBus definition in the Rev. 1.3 specification allows for basic voltage and temperature monitoring and fault reporting functions over the AVSBus, which status then can be relayed by the POL to the SMC/PMC via the PMBus.

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