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Configuration for power systems based on PMBus 1.3

19 Mar 2014  | Michael Jones

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In its present form, the Rev. 1.3 spec defines only a single point master and single point slave for the AVSBus. With the rail identification field in the AVSBus protocol, it is possible to use one port on the AVS master and one port on an AVS slave controller which has multiple phases and/or multiple rails (up to 15). For low-performance systems, the AVSBus can be implemented with only two wires instead of three. In this case, packet checking, monitoring, and fault reporting are not available.


Case 3: Embedded PMC with AVSBus
In the next example, the PMC is embedded as a sub-system within the logic chip, which is the load of the power supplies. Normally it would be desirable to have a separate voltage rail (such as an always-on standby rail, marked "Bias" in the diagrams) power the PMC to avoid issues with power up and down control.




Case 4: Embedded PMC, External SMC
In the next example, the power management functions are embedded in the logic chip, but the system management functions (showing functions such as fan and interlock monitoring) are a separate sub-system outside the FPGA. Note that this configuration may require a multi-master PMBus implementation, depending on the amount of control authority given to the PMC and the SMC.




Aspects not addressed by PMBus 1.3
While the Rev. 1.3 PMBus spec addresses the most likely cases for controlling the power to a high-density logic device, there are still many considerations not addressed by the specification. The implementation of these items is for now left to the user.

1. Point to multi-point AVSBus. As noted before, the PMBus+ spec only defines a single master and a single slave on the AVSBus. Any other configuration, such as multiple AVSBuses or multiple-slave power controllers in parallel on one AVSBus-controlled rail, will need some custom engineering work outside the scope of the specification.

2. Command forwarding over AVSBus. Basic status and voltage setting commands are available over the AVSBus, but general forwarding of other PMBus commands (such as configuration information or device ID strings) is not yet supported by the PMBus specification. There is presently no provision for forwarding any arbitrary data from the POL to the logic device via AVSBus.

3. Frequency coordination between PMBus and AVSBus. The basic assumption in the introduction of the AVSBus is that the AVSBus is significantly faster than the PMBus. This relationship in the bus clock frequencies should be maintained for proper completion of AVSBus transactions (including error checking) while PMBus transactions are still in progress.

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