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Micron patent reminiscent of IBM's latent image memory

13 Mar 2014  | Ron Neale

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The Micron version of the SRAM-PCM hybrid uses the latent image effect by putting a PCM cell in each side of the cross-coupled SRAM cell. Each hybrid SRAM cell has two distinctly separate circuit blocks, encircled in blue or brown in the figure below, each with its own read/write programming input.

In the patent, the Micron inventor describes the operation of the memory cell as requiring one of the PCM devices to be in the set (low resistance) state and the other in the reset (high resistance) state. This provides the necessary high or low resistance difference between the two branches of the SRAM circuit that is required to ensure the cell will remember the latent image data that was loaded into it. To use the background data, the cell and the array will still require the time latency inherent in a latent image memory to ramp the power up. The latent or background data programmed into the PCM and the value of the resistance of each of the two PCM devices must be chosen so that it does not impede the normal SRAM operation of the memory.

Hybrid SRAM cell

It occurred to me that it might be possible to use the latent image effect to create a form of SRAM memory that has the capability to learn without the added circuit complexity required for programming the PCM cells. More recently, IBM spent a lot of effort and ingenuity to deal with the problem of drift that occurs in the high resistance state of PCM memory cells. This is an especially troubling problem when attempts are made to use PCM in a multi-level mode. This drift in resistance occurs naturally, and its rate varies as a function of the local thermal environment.

It might be possible to use this effect, or a similar effect in other materials, to create a memory array that remembers its most often used data state in the form of a latent image. The way this might be achieved for PCM material is to construct a hybrid resistor that consists of a normal resistance material in parallel with a resistor film of chalcogenide material. The implementation would require intimate contact between the two resistors. Then, any current passing through the resistance combination would by thermal coupling cause the rate of drift towards higher values of resistance to change and, because drift is essentially an annealing process, increase the rate, causing a change in the total value of the two resistors in parallel to move to a higher value.

Shown on the right hand side of the figure below is an example of a simple version of the of the proposed Learning Latent image-SRAM (LLi-SRAM) circuit, the hybrid resistors are shown in each branch of the cross-coupled SRAM cell circuit. The resistors consist of a film of chalcogenide in a suitable resistance state, achieved during processing, overlaid on another resistance material.

Learning Latent image-SRAM circuit

On the left hand side is an imagined sequence of operation with the learning process taking place. Initially both resistors, the red and blue lines, drift together. Then, power is applied and the SRAM is operated in the normal manner. However, the highest rate of drift will be determined by the side of the SRAM that spends most of the time in its conducting state. At the end of the period, off operation power is removed and the chalcogenide material of both resistors drifts in the normal manner. When the power is ramped up, the data contents of the memory are determined by the latent image determined by the difference in resistance value between the two resistors.

The next step in time is what happens when a change in temperature to a higher value occurs. This will mean that the effects of annealing and the temperature coefficient of resistance will compete, the high value of the temperature coefficient of resistance of the chalcogenide material will dominate, and the resistance of each resistor will decrease. Then again without power the drift will continue at a constant rate for both resistors.

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