Path: EDN Asia >> Design Centre >> IC/Board/Systems Design >> Digital-analogue combined IP design, verification
IC/Board/Systems Design Share print

Digital-analogue combined IP design, verification

09 Apr 2014  | Tejbal Prasad, Sachin Jain, Arun Barman

Share this page with your friends

Applications today increasingly rely on capturing and processing real time data, be it in the form of stream of audio, video or radio data or real time data coming from various sensors such as temperature, pressure and safety monitors, etc. This is leading to an increase in the number of analogue IP content in the device. Most of these analogue IPs have a digital controlling logic associated with them that allows for the configuration of these analogue blocks for required configurations as well as facilitating the transfer of captured data to and from the core within the chipset.

With the increase in complexity and the content of these analogue blocks, there is an enhanced focus to move more and more functionality, wherever possible, into the Digital domain which allows faster modifications, easy reuse and portability across technology nodes. Having said that there are inherent challenges associated with such Digital-analogue combined IPs, referred to as Mixed Signal IPs hereafter, both in Design and Verification in order to robustly signoff such IPs at block verification level for integration in any SoC.

This paper discusses in detail these challenges and details certain steps that should be followed for faster and robust verification signoff of such Mixed Signal IPs.


What is mixed-signal IP?
An IP is called mixed-signal when it consists of both analogue circuits and Digital logic. The analogue circuit is delivered as a hard-macro in Graphic Data System (GDS) format and the digital logic is delivered as soft program at RTL level written in VHDL, Verilog or System-verilog. The combined part is delivered as a Digital-analogue (DA) block for integration at the System On chip (SoC) level.


Figure 1: Mixed-signal IP block.


Typically the Digital part of a Mixed Signal IP enables following functionality:

User configurability: It allows for configuring the programming Registers of the Mixed Signal IP. All the parameterisation – both static and dynamic are handled by this block.

Communication with the analogue block: This part of the logic is more challenging. This logic controls and responds to the analogue part of the IP. The analogue part could be as simple as just one simple analogue comparator or a very complex one like multiple comparators, analogue multiplexes or phase locked loops; however analogue always works as per the configuration of the digital model. An example is a 2 input analogue Comparator logic where the inputs are provided by the digital interface which also controls the duration until these inputs are exposed on the analogue interface. The digital logic also takes care of these timing aspects of these analogue circuits.


Challenges in design of mixed-signal IP
By the very mixed (Digital-analogue) nature of the Mixed-signal IPs, there are certain challenges associated with the Design Verification of these IPs. In the subsequent sections we will discuss in detail each of them and provide certain guidelines. Note that these guidelines are quite generic and indicative only and should be customised on a case to case basis to fit the specific IP needs. These issues are different depending on the design phases of the IP. Key areas to take care are:

Interface between analogue and digital: The interface signals between analogue and digital need some extra care at the design level to remove issues created inside analogue circuit due to the nature of digital design.

Digital logic works with sequential elements like a Flip-flop and combinational logic gates along with some asynchronous inputs that control certain functionality.

1 • 2 • 3 • 4 Next Page Last Page


Want to more of this to be delivered to you for FREE?

Subscribe to EDN Asia alerts and receive the latest design ideas and product news in your inbox.

Got to make sure you're not a robot. Please enter the code displayed on the right.

Time to activate your subscription - it's easy!

We have sent an activate request to your registerd e-email. Simply click on the link to activate your subscription.

We're doing this to protect your privacy and ensure you successfully receive your e-mail alerts.


Add New Comment
Visitor (To avoid code verification, simply login or register with us. It is fast and free!)
*Verify code:
Tech Impact

Regional Roundup
Control this smart glass with the blink of an eye
K-Glass 2 detects users' eye movements to point the cursor to recognise computer icons or objects in the Internet, and uses winks for commands. The researchers call this interface the "i-Mouse."

GlobalFoundries extends grants to Singapore students
ARM, Tencent Games team up to improve mobile gaming


News | Products | Design Features | Regional Roundup | Tech Impact