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Blurred line between scopes and on-die instruments

14 Apr 2014  | Eric Bogatin

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After the CDR algorithm, the same DFE filter on-die is implemented in the scope to replicated the final eye opening that would appear at the receiver. This filter will take a fraction of a few previous bits and add them to a later bit. The fraction of each prior bit is the "tap coefficient." The coefficient values used in the scope can be selected as the same ones used on-die, or optimised based on the maximum eye opening. Figure 3 shows an example of the impact on the measured eye after the CDR and DFE filter are applied in the scope.


Figure 3: Final signal emulated by the scope based on the CTLE, CDR and DFE features that would be implemented on-die at the RX.


On-die oscilloscopes
Another approach taken by some semiconductor providers is to add oscilloscope functions on-die. The two leading FPGA vendors, Xilinx and Altera, have implemented "embedded instruments" on their latest 28 Gbit/s designs.

In the Xilinx ChipScope Pro family of IP tools, internal circuitry samples the on-die signals at various locations and performs analysis to evaluate signal quality, margin and bit error ratios. The Eye Scan tool allows the export of the sampled eye after the DFE filter to show the eye the receiver actually sees. Figure 4 illustrates where this is implemented in the receiver.


Figure 4: Implementation of the Xilinx Eye Scan, part of the ChipScope Pro IP suite available on all receiver channels in the latest Virtex 7 FPGA designs.


"The Eye Scan results provide important information for validating the design of each channel across voltage, temperature and process," Luis Bielich, applications engineer with Xilinx said. "Along with the ability to validate the design of a channel, Eye Scan also provides a very high level of debug information not previously available in FPGA families."

Altera's version of on-die instrumentation is the EYEQ IP core. The signal is sampled internally after the equaliser and the clock data recovery circuitry. A sampler is used to select 32 horizon and 64 vertical measurements to recreate the eye as it would appear into the deserialiser. Figure 5 shows how EYEQ is implemented.


Figure 5: Block diagram of the Altera EYEQ IP block implemented at the RX (top) and the resulting eye showing the time and voltage sampling positions (bottom).


"This architecture provides non-destructive measurement capability to simultaneously measure both bit errors and eye samples," Lux Joshi, product manager for Stratix V FPGAs at Altera said. "In addition to collecting samples at various sampling times and voltage levels, a hardened serial bit checker allows reconstruction of eye measurements as well as BER contours using either random data or repeating data patterns. This information provides key insights into link margin in system."

When interconnects distort signals so much that they become totally unrecognisable and unusable, new approaches have to be implemented to measure signal integrity. New features are making oscilloscopes look more like the silicon they are testing and the silicon now looks more like the instruments that test them.


About the author
Eric Bogatin is a signal-integrity evangelist at Teledyne LeCroy. He holds an SB degree in physics from MIT and a PhD in physics from the University of Arizona in Tucson. He has been active in the signal-integrity industry for more than 30 years, writing articles and books and teaching classes.


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