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Mentor EVP transforms into a data centre resource

14 Apr 2014

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Mentor Graphics Corp. announced the Mentor Enterprise Verification Platform (EVP), which combines Questa verification solutions, Veloce OS3 global emulation resourcing technology and Visualizer, a powerful debug environment, into a globally accessible, data centre resource.

The Mentor EVP features global resource management that supports project teams around the world, maximising both user productivity and total verification return on investment. The Mentor EVP delivers performance and productivity improvements ranging from 400X to 1,000X.

"Mentor's verification vision is to deliver an environment where the verification process is completely abstracted from the underlying verification engines from first design thoughts, through silicon, to final product," said John Lenyo, VP and general manager, Design Verification Technology Division, Mentor Graphics.

Global data centre resource

Veloce OS3 and Mentor VIP transform emulation into a global data centre resource.

To leverage the investment in emulation and allow it to serve as a true enterprise verification resource, emulation must undergo a transformation from project-bound engineering lab instrument to data centre-hosted global resource. This transformation begins by eliminating the In-Circuit Emulation (ICE) tangle of cables, speed adaptors and physical devices, replacing them with virtual devices.

The Veloce OS3 VirtuaLAB peripherals are reconfigured instantly to support multiple projects and rapidly shifting priorities. This is possible because VirtuaLAB is hosted on standard data centre computers, not proprietary hardware targets.

The OS3 Enterprise Server efficiently manages the global emulation resources, consolidating them to commercial queue managers as a single entity. The Enterprise Server determines the most efficient location to run each job and immediately serves high-priority jobs by temporarily suspending jobs of lower priority.

Veloce OS3 also delivers verification features to the emulator, including PSL/SystemVerilog assertions, functional coverage and UPF for low power. This enables a high-performance coverage closure flow and pre-silicon performance analysis of critical SoC sub-systems running application software.

To maximise testbench reuse, the Mentor Verification IP, built using standard UVM/RTL, is designed for both simulation and acceleration modes. These capabilities are in place for a smooth transition from simulation to emulation, allowing for a 1,000X performance boost over simulation alone with no loss of functionality.


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