Path: EDN Asia >> News Centre >> IC/Board/Systems Design >> Krivi samples DDR PHY with ARM CoreLink Technology
IC/Board/Systems Design Share print

Krivi samples DDR PHY with ARM CoreLink Technology

22 Apr 2014

Share this page with your friends

Krivi Semiconductor, a start-up located in Bangalore, India, has unveiled its initial working silicon of a 28nm DDR3 PHY. The new Krivi DDR3/3L PHY with ARM CoreLink DMC-400 Dynamic Memory Controller is JEDEC compatible, feature rich and supports maximum speeds of up to 2.133Gbit/s.

Synthesisable and PnR friendly, this latest RTL from Krivi supports custom floor-planning to suit modern SoC providers who require faster-time-to-market or more stringent overall PHY area requirements. Numerous patent-pending, jitter tolerant training algorithms and superior analogue components will enable Krivi SoC partners to use DDR without using an oscilloscope during chip bring-up.

Krivi offers advanced training to correctly align READ and WRITE data bits at the centre of data strobe without any side band signalling. Its innovative automatic write-levelling caters to all types of DIMMs. Dynamic gate training maintains on-track capture of read data strobe without consuming any system bandwidth. All the training could be independently performed on each of the available chip selects.

Krivi PHY corrects up to a one-quarter clock cycle of skew in each of the READ and WRITE data bits. This virtually alleviates the necessity of tightly matched PCB routing requirements and recovers timing margin from DRAM READ/WRITE budgets.

Krivi's DDR PHY requires very little register programming but offers extensive registers for power and performance fine-tuning. Every DLL and training value is observable and could be bypassed if required. To minimise power integrity challenges, PHY incorporates mechanisms for in-rush current control during OTF data width selection and low power entry/wakeup. The Krivi PHY offers advanced low power modes and automatic re-calibration post wakeup. IO retention allows shutdown of PHY supplies with the exception of a small live IO domain to keep DRAM in self-refresh for data coherency.

The PHY offers loop back BIST for all the analogue intensive paths including READ, WRITE, and ADD/CMD clubbed with its comprehensive DFT solution.

The PHY uses a DFI interface and provides programmable options to hook to virtually any memory controller. Krivi PHY is extensively verified for the ARM ecosystem including ARM memory controllers.




Want to more of this to be delivered to you for FREE?

Subscribe to EDN Asia alerts and receive the latest design ideas and product news in your inbox.

Got to make sure you're not a robot. Please enter the code displayed on the right.

Time to activate your subscription - it's easy!

We have sent an activate request to your registerd e-email. Simply click on the link to activate your subscription.

We're doing this to protect your privacy and ensure you successfully receive your e-mail alerts.


Add New Comment
Visitor (To avoid code verification, simply login or register with us. It is fast and free!)
*Verify code:
Tech Impact

Regional Roundup
Control this smart glass with the blink of an eye
K-Glass 2 detects users' eye movements to point the cursor to recognise computer icons or objects in the Internet, and uses winks for commands. The researchers call this interface the "i-Mouse."

GlobalFoundries extends grants to Singapore students
ARM, Tencent Games team up to improve mobile gaming


News | Products | Design Features | Regional Roundup | Tech Impact