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Scriptable interface accelerates tool dev't

16 May 2014

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Invionics unveiled the VRDM Development Platform that layers a rapid development interface on top of Verific's industry-standard, IEEE-compliant SystemVerilog and VHDL parsers.

"VRDM lets designers use the features they expect and languages they know to accelerate their next EDA product or custom tool development," said Michiel Ligthart, Verific's president and COO.

To gain advantage in highly competitive markets, semiconductor and system design companies increasingly are building their own in-house design tools and flows. The VRDM Development Platform reduces costs and accelerates development of these tools and flows by providing a high-level, easy-to-use, scriptable interface to Verific's parsers.

"We set out to accelerate design tool and flow developments that require Verific's SystemVerilog and VHDL parsers, a market we knew could really benefit from automation," says Dr. Brad Quinton, Invionics' CEO. "Our engineering team has extensive real-world IC design experience coupled with a deep understanding of EDA software development and Verific's parsers, an impeccable background to design the VRDM Development Platform."

VRDM is designed to be intuitive and efficient to designers and CAD engineers. It can be used to build a variety of design tools and flows, such as static verification, linting, design for test (DFT) insertion, FPGA prototyping pre-processing, power management insertion, and more. With an intuitive Python or Tcl application programming interface (API), VRDM enables quick development of high value-add internal tools and utilities. With VRDM knowledge of C++ is not a requirement.

Additional key functionality includes advanced regular expression-based design search, detailed interactive design reporting, an XML export capability and support for the Synopsys Design Constraint (SDC) format.

Verific's software is the front end to electronic design automation (EDA) and FPGA tools for analysis, simulation, verification, synthesis, emulation, and test of register transfer level (RTL) designs. Its Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl APIs. Verific's software is distributed as C++ source code and compiles on all 32- and 64bit Unix, Linux, and Windows operating systems.




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