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Synopsys outs PCI Express 4.0 IP solution

23 May 2014

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Synopsys Inc. has unveiled the industry's first complete PCI Express 4.0 IP solution, consisting of DesignWare PHY, controllers and verification IP (VIP) targeting enterprise computing applications such as servers, networking, storage systems, and solid state drives (SSDs).

The PCI Express 4.0 specification, the next generation of the PCI Express I/O standard, doubles throughput to 16GT/s and is currently at a preliminary revision 0.3 within the PCI Special Interest Group (PCI-SIG). The DesignWare IP for PCI Express 4.0 architecture enables easy SoC integration of 16GT/s performance and the power-saving features defined in the PCI Express 4.0 specification.

Based on proven technology in the DesignWare IP for PCI Express 3.0, 2.1, and 1.1 architectures, the DesignWare IP for PCI Express 4.0 architecture allows designers to quickly incorporate the new PCI Express 4.0 standard into their products with less risk and improved time-to-market.

The DesignWare PHY IP for PCI Express 4.0 architecture will support full-featured bifurcation and aggregation, offering designers the flexibility either to configure the PHY macro into multiple individual links at 2.5 GT/s, 5 GT/s, 8 GT/s, or 16GT/s, or to aggregate the PHY macro up to 16 lanes. For increased signal integrity at high-speed data rates across legacy channels, the PHY analogue front-end will include 5tap DFE, continuous time linear equalisation (CTLE), and feed forward equalisation (FFE) with advanced algorithms for link initialisation and adaptation.

As power reduction is a key requirement in many markets, the DesignWare PHY IP will reduce both active and standby power consumption through advanced techniques including L1 sub-states. Support for Separate Refclk Independent SSC (SRIS) will allow the use of cables to enable a new class of PCI Express applications outside of the system.

The Synopsys Verification IP for PCI Express architecture will be available to thoroughly verify designs based on the PCI Express 4.0, 3.0, 2.1 and 1.1 specifications. It will be fully configurable to support verification of PCI Express technology end-points, switches, and root complex devices at the PIPE or serial interface. With this comprehensive set of protocol, methodology, coverage, verification, and productivity features, designers will be able to achieve rapid verification closure of their designs using PCI Express technology.




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