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Benefits of reuse in pre-silicon validation

23 Jun 2014  | Amitesh Khandelwal, Ayushi Agarwal

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The IC design industry always aims to deliver first-pass silicon, which means finding most, if not all, of the potential defects before tape-out. This is extremely difficult due to increasing design complexity, clock speeds, multi-layered software, and shrinking technology and cycle time. Each re-spin of the silicon may cost a company millions of dollars and a lot of wasted time and effort. With more and more third party IP being used in the SoC to shorten time-to-market, the task of finding bugs before silicon becomes more difficult due to limited knowledge of the external IP by the SoC engineers.


The usual approach
SoC teams have typically relied on pre-silicon emulation to ensure first-pass silicon in such a complex and dynamic environment. The emulation platform enables closer to real time software development & accelerated simulation run time to expose more defects early in the cycle. It also provides a good framework to develop post silicon validation test suite.

However the programming framework of pre-silicon environment is typically similar to post silicon validation making it difficult to run verification patterns as is. Some of the differences include

Verification C-APIs write to fix memory locations to enable snooping by Testbench to generate Info prints.

Clocking macros do not work since clock sources are analogue and stubbed out in emulation platform.

Memory map header files may be different in format or content.

Due to these limitations verification team often is not able to leverage the advantages provided by the emulation platform without having to make changes in the existing test suite to address the differences highlighted above.


Proposed methodology
In this paper, we propose a methodology to bridge the gap between SOC verification and Pre-silicon validation to reduce the debug effort and the run-time of the verification sequences.

We will use an Audio Sub-system as a case study to demonstrate this methodology.

This sub-system is responsible for recording and playing back the audio signals. It has two ADCs and three DACs among various other components. The Audio data from the external world can be recorded using the two Audio ADCs and recorded data can be played back using the three Audio DACs.

Functionality can be checked by using Analogue or Digital loopback in which we loopback the analogue/ digital data from DAC to ADC and vice-versa.

To enable merger of pre-silicon and verification environment a component we called an Adapter was developed.


The adapter
Since there is a considerable difference between pre-silicon emulation and verification environment, for more efficient use of the resources and to reduce the debug gap, we tried to create a flow in which there is no change in coding sequence, logical or syntactical. The original sequence used in verification is used as is by adding an Adapter in pre-silicon emulation.

The Adapter is a collection of functions written in C which acts as a bridge between verification and validation programming environments. This includes:

 • Redefinitions of read-write functions.
 • The memory map used in the verification.
 • SoC Level reusable functions, e.g., clock enables, delays etc.
 • Common display and logging functions e.g., printf, info and error macros.
So in a nutshell, Adapter redefines all the functions which are used in verification but not available in pre-silicon environment directly. This one time effort enables reuse of all the tests available in the verification environment. It also enables development of complex sequences and use cases which otherwise take too long to simulate and mature in pure verification environment.


The audio sub-system and the testbench
Implementation of analogue is a limitation of emulation so a different model of the sub-system is used in the emulation which does not need analogue inputs/outputs to perform the functional tests.

Analogue loop-back is implemented from line outputs to input amplifiers. It is used to test the operation of each stereo DAC and ADC signal paths and the connectivity of the IP to the rest of the SOC.

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