Path: EDN Asia >> News Centre >> Computing/Peripherals >> Flash Summit bares future of memory
Computing/Peripherals Share print

Flash Summit bares future of memory

11 Aug 2014  | Rick Merritt

Share this page with your friends


Looking beyond NAND, Part 2

Just around the bend in an out-of-the-way corner of the Smart Modular both, Everspin Technologies showed its ST-MRAM chips in a mini-DIMM card. Separately, start-up Mangstor announced it will use one of Everspin's 64Mbit chips to buffer data writes to NAND on its new MX6000 memory card.

The good news for Everspin is it is delivering non-volatile memory at DDR3 DRAM speeds, although boot up latency still drags a bit at 50ns to 70ns. The bad news is it's a 64Mbit chip at a time when NAND vendors are trying to get their 128Gbit designs out the door.

Everspin has plenty of room to scale. Its current chip is made in a 90nm CMOS process, and it believes a future 28nm chip could hit Gbit densities. But don't expect such a big leap anytime soon. Stair step increases are expected about every 12 to 18 months, making it hard to catch up in density with leading-edge flash.

In addition, engineers must do some custom programming of the DDR3 controller for some unique timing and paging characteristics in the current Everspin design.

Flash Memory Summit

Don't count the next-gen architectures out, says Janukowicz of IDC. "We continue to see a lot of investment sprinkled across variety of non-volatile memory types, but the challenges to surpass NAND and now 3-D NAND are great," he said.


DRAM battle shifts into fourth gear, Part 1

Diablo Technologies announced plans to upgrade its flash controller to DDR4 speeds and feeds. The company launched its DDR3 flash card solution last year and gained support from IBM.

 Michael Takefman

One of the goodies in the DDR4 upgrade is a so-called Nano-Commit feature that can quickly transfer DRAM data to flash at near-DRAM speeds. High frequency traders like the feature because their financial transactions are not completed until they are stored in non-volatile memory or storage.

Diablo's current developer's kit uses an FPGA to translate between DDR3 and DDR4 interfaces. An ASIC version will tape out early next year, but a fully qualified card will not be ready until late 2015.

The final DDR4 product will drive Diablo's already low latency down another notch, said chief architect Michael Takefman (above).


 First Page Previous Page 1 • 2 • 3 • 4 Next Page Last Page


Want to more of this to be delivered to you for FREE?

Subscribe to EDN Asia alerts and receive the latest design ideas and product news in your inbox.

Got to make sure you're not a robot. Please enter the code displayed on the right.

Time to activate your subscription - it's easy!

We have sent an activate request to your registerd e-email. Simply click on the link to activate your subscription.

We're doing this to protect your privacy and ensure you successfully receive your e-mail alerts.


Add New Comment
Visitor (To avoid code verification, simply login or register with us. It is fast and free!)
*Verify code:
Tech Impact

Regional Roundup
Control this smart glass with the blink of an eye
K-Glass 2 detects users' eye movements to point the cursor to recognise computer icons or objects in the Internet, and uses winks for commands. The researchers call this interface the "i-Mouse."

GlobalFoundries extends grants to Singapore students
ARM, Tencent Games team up to improve mobile gaming


News | Products | Design Features | Regional Roundup | Tech Impact