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JEDEC bares low-power memory standard

27 Aug 2014

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Several other steps were taken to save power. The operating voltage was reduced from the 1.2V of previous generations to 1.1V. Also, the standard was specifically designed to enable power-efficient operation at a wide range of frequencies. The I/O can operate in un-terminated mode at low frequencies with a reduced voltage swing, and the standard allows rapid switching between operating points so the lower frequency operation can be used whenever possible.

This rapid switching is enabled by the addition of frequency set points (FSPs). LPDDR4 specifies two FSPs, which are copies of all the DRAM registers that store operating parameters, which might need to be changed for operation at two different frequencies. Once both operating frequencies are trained and the parameters stored in each of the two corresponding FSPs, switching between the frequencies can be accomplished by a single mode register write. This reduces the latency for frequency changes and enables the system to operate at the optimal speed for the workload more often.

"It supports end-user flexibility," noted Vuong. "Some designers like to run their devices as fast as they can and then put them to sleep. Others like to run at lower frequencies—and lower power—when possible. A process might take a little longer but that's a trade-off they're willing to make. We designed LPDDR4 to be flexible enough to allow the end-user to decide what they want to do." With that flexibility comes superior performance—an LPDDR4 device, at a similar data rate, will consume less power than an LPDDR3 device.


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