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RDIMM vs LRDIMM: What changed for the better?

10 Sep 2014  | Douglas Malech

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As an example shown in figure 8 for Gen1 DDR3 server platforms (Gen 1 DDR3, circa 2010), the host controller was largely "rank unaware" when operating in a rank multiplication mode. This meant that the host had to always assume it was switching to a different DRAM for the next read and, therefore, account for time to disable one DRAM and enable the other DRAM onto the same data bus. Conversely, this meant that such controllers were not able to use the fastest timing when doing back-to-back read transactions to the same logical rank. This resulted in up to 25% penalty on the data bandwidth upon reads. When compared to an RDIMM solution on fully populated 24 slot systems operating at the same speed, LRDIMM provided only 70% of the memory bandwidth.

In Gen2 DDR3 server platforms (Gen 2 DDR3, circa 2012), controllers became aware of the physical ranks behind the data buffer. They were able to request data from the memory far more efficiently because back-to-back reads and writes to the same DRAM could use the fastest timing. They also overcame some other limitations to improve the speed. So, Gen2 DDR3 server platforms achieved a speed improvement over Gen1 DDR3 server platforms, but more importantly, closed the bandwidth gap with a corresponding RDIMM solution. The only remaining penalty on the DDR3 platforms was due to the component and trace length latencies mentioned above.


Figure 7: Rank Multiplication for 3 DIMMs per memory channel.


On DDR4, the distributed buffer architecture reduces the latency through each of the much smaller distributed data-buffers. Further, it allows for the memory controller to be able to hide the much lower latency in its micro-architecture.

Eco-system improvements on DDR4 LRDIMM have continued the trend of significantly improving the memory bandwidth along with the channel speed. This is poised to increase the usefulness of LRDIMMs in comparison to RDIMMs across a wider array of applications, whether capacity intensive, or bandwidth intensive, or both.


Figure 8: Bandwidth improvement normalized with RDIMM at the same speed with generations for memory controllers.


Figure 8 summarises the results of improvements on successive enterprise server platform generations from actual experiments performed at IDT's validation lab. 3DPC at 1866 can potentially be realised using LRDIMMs while only 3DPC at 1600 can be realised using RDIMMs. Owning to these improvements, we expect some server manufacturers who have always configured their server platforms for speed to also consider 16GB LRDIMM as another reduced cost alternative to the higher capacity 32GB LRDIMM option. In essence, DDR4 LRDIMM is not just for capacity. It is for capacity as well as bandwidth.


About the author
Douglas Malech is the product marketing manager for memory products at IDT. He began his career in high technology as a radar systems design engineer working at Raytheon Company and moved into instrumentation design at Credence Systems Corporation. He has spent more than 30 years in various roles in engineering, marketing, and business development at Raytheon, Credence Systems, Maxim Integrated Products, and Integrated Device Technology. Douglas received a BS in engineering science from Tufts University and an MS in computer, information, and control engineering from the University of Michigan.


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