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How to prevent damage when testing thin devices

19 Sep 2014  | Taqi Mohiuddin

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People prefer light and thin mobile devices, which is why Apple's iPhone 6 is thinner than previous models. Thinner devices drive the development of advanced packaging technologies, but traditional epoxy plastic packages are inadequate for creating these extremely thin devices because their package footprint is up to six times bigger than the chips they house.

The solution to this problem is CSPs (Chip Scale Packages), which are the same size as the chips themselves. CSPs attach directly to circuit boards using solder balls. Unfortunately, the small size of CSPs make them fragile and susceptible to damage during handling. As a result, the semiconductor manufacturing industry needs new methods to qualify devices so that engineers understand failures and failed devices can be screened.


Thin is in

Apple's iPhone 6 (Figure 1), is 6.9mm thick. That's down from 7.6mm for the iPhone 5 and 8.8mm for the iPhone.

iPhone 6

Figure 1: At 6.9mm, the iPhone 6 is thinner than its predecessors. (Source: International Business Times)

Because batteries and screens aren't getting thinner, the thickness of the packaging and substrate board must shrink. That's driving the move to CSPs. (Figure 2).

Small packaging

Figure 2: Packages are getting smaller, so the qualification challenge is getting larger.

According to Brandon Prior of the research firm Prismark, the iPhone 5S was the first mobile device to use 50µm line/space (L/S) and CSPs on an 0.4mm pitch. Prismark forecasts that more than 28 per cent of CSPs and WLCSPs (wafer-level CSPs) will be at 0.4mm or less by 2018.

Qualcomm's senior director of package engineering, Steve Bezuk, discussed packaging challenges at the IMAP Device Packaging Conference 2014, saying that while very few packages during the late 2000s were WLP, this category now accounts for nearly half of IC packages.

CSP substrates keep getting thinner. The SEMI global industry association says that today's leading-edge CSP substrates have 15µ lines and spaces, and are moving towards even finer lines and spaces so they can handle fine bump pitch of less than or equal to 110µ. In its report titled Global Semiconductor Packaging Materials Outlook – 2013-2014, SEMI said that substrate makers are targeting 5µ lines and spaces in 2015. They are also looking at 40µ via diameters in the build-up layers. The report said that core layers are being fabricated with 12µ lines and spaces, with vias as small as 50µ and capture pads as small as 110µ.

These and related trends make CSPs increasingly difficult to handle. Thus, they're even more prone to damage prior to and during the qualification stage of production. In general, any CSP reliability qualification process must address four key issues:

  • Handling
  • Incoming and outgoing quality control (IQC/OQC)
  • Socketing
  • Unbiased stress testing

A CSP's exposed silicon material is raw and very brittle. Thus, it can suffer from stress cracking during handling. Such cracking can create imperfections in the silicon matrix, which can cause the resulting cracks to propagate with the additional stress during qualification processes. These and other dynamics make differentiating between CSP failures induced by qualification-related stress tests and by handling extremely difficult. The problem becomes even more challenging at the high production volumes of mobile devices.


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