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Overcoming the clock tree design challenge

07 Oct 2014  | Baljit Chandhoke

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A second IDT5P49V5901 (Device # 4) supports a second system switch with two programmable frequencies, one 125MHz with LVPECL or LVDS output, and a second at 125MHz with 1.8V LVCMOS output. This 10GBASE-T PHY is a low power, high performance 10G/1G/100M transceiver designed to perform all the physical layer functions for 10GBASE-T transmission over 100m of twisted pair cabling. The PHY integrates Energy Efficient Ethernet (EEE), 1588v2 and MACsec and adds advanced mixed-signal RFI cancellation techniques and integrated MDI filtering. The switch supports numerous system interfaces including full KR (with auto-negotiation), XFI, RXAUI, XAUI and SGMII.

Finally, the design includes two more IDT5P49V5901 programmable clock generators to support a high-performance communications processor. Featuring multiple cores, the processor combines a high performance compute engine with a variety of datacomm and networking interfaces. In this instance one IDT5P49V5901 (Device #2) provides four selectable programmable frequencies, two at 100/125 or 156.25MHz and two at 100 or 125MHz with HCSL outputs. Another IDT5P49V5901 (Device #3) generates three or four frequencies, depending upon implementation. This particular clock generator also provides a 100MHz HCSL channel to a 2-output low power PCIe buffer.


Better performance, lower power
The proposed solution met the customer's stringent jitter requirements with a best-in-class 0.7 ps RMS phase jitter over the full 12kHz to 20MHz integration range. This spec meets both PCI Express Gen 1/2/3 and 1G/10G Ethernet requirements. At the same time, IDT's proposed solution reduced operating power expense and simplified system thermal management by operating at less than 100 mW core power. This low power spec on the VersaClock 5 helped reduce power requirements for the clock tree by more than 75 per cent compared to the preceding design. The new design paid off in terms of footprint and BoM cost as well. By consolidating multiple crystals and oscillators into a single piece of silicon, the new clock tree reduced component count and board space. Moreover, the shorter lead times of a silicon solution compared to crystals and oscillators, and the immediate availability of samples and eval boards, helped shorten the development cycle and accelerate time-to-market.

The proposed clock tree's inherent design flexibility also proved attractive to the customer. With over a dozen independent frequencies and various differential and single-ended outputs, programmability was a high priority. While the VersaClock 5 is in-system programmable via I2C, it also features four banks of OTP memory. This opened up new programming options. As an example, the switch supported by device #1 needed to be switchable across two frequencies (156.25MHz and 161.1328125MHz). By programming the different OTP banks at 156.25MHz and 161.1328125MHz, the customer could switch from frequency to frequency and output to output in different configurations using select pins instead of I2C.

Moreover, to help simplify setup of these complex configurations, the customer was able to use IDT's Timing Commander software platform, which allowed them to configure and program the VersaClock 5 via a GUI. With this tool, the customer was able to program four fractional output dividers to provide four independent output frequencies or configure output pairs as differential outputs or two single-ended LVCMOS outputs. The user could also direct the system to program the device via I2C at powerup to override the OTP memory configurations if needed.


Conclusion
As the design example above illustrates, today's high performance data communications and networking systems demand complex timing solutions. Simple discrete devices are no longer adequate. More often than not, designers need sophisticated, highly integrated programmable clock generators that supply a high level of programming versatility while meeting constantly growing requirements for high performance and low power.


About the author
Baljit Chandhoke is a Product Line Manager for Timing Products at Integrated Device Technologies, responsible for new product definition, product line management and interfacing with customers globally to help them meet their design challenges. Prior to joining IDT in 2011, Baljit was Product Marketing Manager at ON Semiconductor and Senior Applications Engineer at Cypress Semiconductor, where he worked on PLL SerDes and Video Equalizers from 2003 to 2006. Baljit completed Executive Education on Managing Teams for Innovation and Success from Stanford in 2014, completed his Master's in Business Administration (M.B.A) from Arizona State University in 2009, M.S. in Telecommunications from University of Colorado Boulder in 2003 and got his Bachelors in Electronics and Telecommunications Engineering from University of Mumbai, India in 2000.


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