Path: EDN Asia >> Design Centre >> IC/Board/Systems Design >> Rigorously tuned compact modelling approach
IC/Board/Systems Design Share print

Rigorously tuned compact modelling approach

02 Dec 2014  | George Bailey

Share this page with your friends

One of most challenging process effects to model has been the degradation of resist profiles due to low-contrast imaging, so one of the most sought after RTC modelling applications today is for 3D resist models to ensure that etch punch-through does not occur. Figure 4 demonstrates the power of the RTC modelling approach to predict the 3D resist effects. Here the 3D resist diffusion terms were turned on and off to confirm the RTC model approach would predict as well as a rigorous model. The profile comparison and CD distribution plots on the left were generated with the diffusion terms turned off, and the profile comparison and CD distribution plots on the right were generated with the diffusion term turned on. The OPC model without the diffusion term generated a CD variance of 8.9nm root-mean square (RMS), and the OPC model with the diffusion term turned on generated a CD variance of 0.33nm RMS. These results demonstrated the RTC modelling approach was very effective in emulating rigorous-like predictability for large layout applications.


 OPC model compared to a rigorous model

Figure 4: Profile and CD distribution comparison of an OPC model compared to a rigorous model demonstrate the effectiveness of the RTC modelling approach. The left profile and CD distribute is an OPC model with the physical term for resist diffusion turned off and the right profile and CD distribute is an OPC model with the physical term for resist diffusion turned on.


Another highly demanded application for RTC modelling is the optimisation of assist features (AF) to maximise process windows. The objective for AF optimisation is to generate the largest AFs as possible without causing them to print. In figure 5, the RTC model is being utilised to predict the onset of AF printing on the wafer. For this test, we took a line/space pattern (cyan), varied the pitch from 180nm to 280nm in 10nm increments and then varied the AF (pink) widths from 14nm to 28nm in 2nm increments. By varying both the line/space pitch and AF, there will be a combination of factors that will eventually trigger AF printing. The image on the left in figure 5 shows where the rigorous and RTC model were both able to predict that the AF would print on an 180nm pitch line/space pattern when the AF width was increased from 16nm to 18nm. The table on the right in figure 5 shows that the RTC model was able to predict AF printing as precisely as the rigorous model for all 11 line/space patterns tested. Again, these results demonstrate how the RTC modelling approach was very effective in emulating rigorous-like predictability.


 Predictability test

Figure 5: This predictability test checks if an RTC model has the same predictive power of a rigorous model. The RTC and rigorous models both predicted when the AFs went from clear to print (C→P) for all pitches as noted in the table.



Conclusion

The RTC modelling approach was shown to be an effective method to address the accuracy and predictability issues caused by insufficient metrology methods and optically-dominated OPC models. These metrology and process complexity problems will become more substantial with the continued push of ArF imaging, so the ability for the RTC modelling approach to adapt to include new metrology and rigorous formats will be vital at the 10nm node and beyond.


References
1. Ulrich Klostermann, "Calibration of physical resist models: methods, usability, and predictive power," Journal of Micro/Nanolithography MEMS MOEMS. (2009).

2. W. Demmerle, T. Schmoeller, H. Song, and J. Shiely, "Rigorously tuned compact models: Extending predictive models to full-chip," Solid State Technology. 57, 22-27 (2014).

3. Y. Fan, C. R. Wu, Q. Ren, H. Song, and T. Schmoeller, "Improving 3D resist profile compact modeling by exploiting 3D resist physical mechanisms," Proceedings of SPIE. 9052, Optical Microlithography XXVII, 90520X. (2014).

4. M. G. Bardon, et al, "Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance," Symposium on VLSI Technology, (2013).


About the authors
George Bailey is the Technical Marketing Director for Synopsys' Mask Synthesis product line.He has over 30 years of semiconductor experience in managerial and technical roles with industry leaders like Texas Instruments, Motorola (now Freescale), Nikon Precision, LSI Logic (now Avago), and Mentor Graphics.George has a BS in Physics and mathematics from Texas State University and an MBA from George Fox University.George holds 11 semiconductor related patents and has published over 30 technical papers and articles.


 First Page Previous Page 1 • 2 • 3


Want to more of this to be delivered to you for FREE?

Subscribe to EDN Asia alerts and receive the latest design ideas and product news in your inbox.

Got to make sure you're not a robot. Please enter the code displayed on the right.

Time to activate your subscription - it's easy!

We have sent an activate request to your registerd e-email. Simply click on the link to activate your subscription.

We're doing this to protect your privacy and ensure you successfully receive your e-mail alerts.


Add New Comment
Visitor (To avoid code verification, simply login or register with us. It is fast and free!)
*Verify code:
Tech Impact

Regional Roundup
Control this smart glass with the blink of an eye
K-Glass 2 detects users' eye movements to point the cursor to recognise computer icons or objects in the Internet, and uses winks for commands. The researchers call this interface the "i-Mouse."

GlobalFoundries extends grants to Singapore students
ARM, Tencent Games team up to improve mobile gaming


News | Products | Design Features | Regional Roundup | Tech Impact