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Demystifying high speed ADC conversion error rate

01 Dec 2014  | Ian Beavers

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When there are no errors detected, the equation becomes much simpler as the right term is equal to zero and the result only depends upon the left term. For a 95% confidence level with no measured errors, we must take only about 3 times the number of samples as the inverse expected CER. Measuring to a 100% confidence level, where CL=1.0 for any CER value, mathematically takes an infinite amount of samples (N) as –ln(0) à infinity.


N*CER = -ln(1-0.95) = -ln(0.05) = 2.996


 Plot of N*CER vs. confidence level and error detection count

Figure 3: Plot of N*CER vs. confidence level and error detection count. Notice that CER testing can continue after a detected error, but only at the expense of an increased number of measured samples to achieve the same confidence level.


Error threshold
All conversion errors within High Speed ADCs are not created equal. Error magnitude is critical as some errors are definitely more important than others. For example, a one or two least significant bit (LSB) error may be within the expected noise floor of the system and may not even impact instantaneous performance. However, a most significant bit (MSB) error, or even a full scale error, could potentially cause a system failure event. Therefore, the CER testing needs to have a mechanism or threshold to grade the severity of the error in the conversion.


 Reconstructed sinewave from ADC samples

Figure 4: A reconstructed sinewave from ADC samples can be seen with a bounded upper and lower threshold limit. When a code exceeds the limit, it is determined to be a conversion error. A benign non-linear outlier sample that is still within the thresholds is not considered a conversion error.


The error threshold for conversion should include the known linearity imperfections of the ADC, along with the clock jitter and other system noise that are outside the capabilities of the converter. This typically sums cumulatively to 4 or 5 least significant bits (lsb), or 16-32 codes of a 14b ADC for any given sample. It may be slightly more or less depending upon the ADC resolution, system performance and the application's error rate requirements. When this error band is used to compare against the ideal value, a sample that exceeds this limit will be counted as a conversion error. In legacy video ADCs, this error was called a 'sparkle code' as it produced a bright white pixel flash on the video screen.

The acceptable converter error rate will largely depend upon the requirements of the signal processing system and system tolerance for errors. For example, a user of a back-yard mobile Bluetooth speaker system may be able to tolerate several errors per hour and not even notice. A mission critical sensor aboard a space satellite may need minimal converter ambiguity, or else satellites might start falling from the sky. Well, maybe not to that severity, but very bad things may start to happen, like poor television reception.

Historical measured GSPS ADC conversion error rates have typically been no better than 1e-14. For an error rate of 1e-12, this means that the converter should not produce a conversion error in 1e12 (1 trillion) samples. An error rate of 1e-15 means that the converter should not produce a conversion error within a span of 1e15 (1 quadrillion) samples. With the high sample rates of today's state of the art converter technology, this may seem large but still manageable to test for CER. However, for a 125MSPS converter with an 8ns sample rate, 1 trillion samples will take 800 seconds (1e12 * 8ns) or about thirteen minutes. 1 quadrillion samples would take 800,000 seconds (1e15 * 8ns) or 9.24 days. For a 95% confidence level in these error rates, we would need to multiply each of those sample durations by 2.996 respectively.


 Plot of CER vs. an Error Magnitude Threshold

Figure 5: Plot of CER vs. an Error Magnitude Threshold. The error threshold limit placed on the testing (in ADC codes) will have an impact on the CER at a given confidence level.


Testing for CER
A simplistic block diagram below depicts how an internal ADC core can be tested for its CER. A relatively slow frequency sinusoid can be used as the analogue input, while sampling at or near the ADC maximum encode rate. The analogue input signal is planned such that the expected absolute difference from one sample to the next is ideally no more than 1 LSB code, neglecting system noise. Ideally, the analogue input signal is slightly larger than full scale, so that all codes of the ADC are exercised. The analogue input and the encode sample rate should be computed such that a long cycle of coherency is established and the ADC is not consistently sampling at the same code levels.


 Two sampling cases

Figure 6: Two sampling cases are shown for CER testing. The top case samples an analogue signal just slightly faster than Fs/2, where only every other sample is compared. Two successive samples are ideally different by no more than one LSB code. The lower case oversamples a relatively slow analogue input such that two adjacent samples are also different by no more than one LSB code.



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