Path: EDN Asia >> Design Centre >> Automotive >> ADC pipeline hardware for multi ADC sampling
Automotive Share print

ADC pipeline hardware for multi ADC sampling

08 Jan 2015  | Kumar Abhishek, Snehal Rathi, Garima Jain

Share this page with your friends

In a real SoC the issue appears to be as shown in figure 2. This issue is what is commonly referred to as a Charge Sharing problem with simultaneous sampling.


Figure 2: Issue with pipeline.


Noteworthy facts about sampling phase of an ADC
Let us try to understand the intricacies of sampling through an ADC with the help of an example. For a data throughput rate of 1Msps on an 80MHz ADC the numbers of cycles taken for total conversion (sampling + conversion) are 80. Out of these 80 clock cycles 26 are taken in the sampling phase (26 being a pessimistic number). If more than one ADC starts charging through the same input voltage source, the capacitor visible to the source becomes twice the value but the R of the path remains the same, which is why there has to be a limit to the number of ADCs. For guaranteeing less than 1 LSB error or 99.99% accuracy the sampling time has to be 10RC. In 10RC, R is the total resistance of the analogue channel, which is basically the sum of package resistance, routing resistance, resistance within the pad and muxing stages. Similarly C is the total capacitance, package+routing+pad+muxing.


Hardware implementation
The proposed solution assures that the sampling of the signal happens through a single pad so that the number of dedicated I/O ports for ADC analogue data sampling can be minimised. The solution ensures that sampling through a single pad happens without any impact of charge sharing between the ADCs in the sub-system. Implementation of this entire logic is done in hardware so that a robust multiple ADC sub-system emerges. Also, a complete ADC sub-system architecture which ensures high accuracy of the data and increased throughput through pipelining without software interventions to do this is certain.

The proposed hardware is comprised of two parts:

 • Firstly, it consists of a Parameterized Hardware architecture to skew the sampling and conversion phases of the multiple ADCs.
 • Secondly, Pipelining Logic which helps to improve the throughput of the sub-system.


Parameterized hardware of the skew logic
This unit of the hardware takes two inputs:

 • The number of ADCs which will be the part of the sub-system
 • A sample start pulse which will trigger the sub-system.

The Skew Logic works as follows:

Depending on the number of ADCs, the hardware logic computes the skew between the beginning of the sampling phases of the ADCs ensuring that each ADC gives data output at the rate of 1Msps and hence the overall sub-system data throughput will be N*1Msps, where N is the number of ADC's. Pipelining logic is finally used to interleave the data coming from the ADCs to achieve this.

A Pulse generator circuit is used to create mutually exclusive sampling phases for the ADCs to avoid charge sharing and loss of sampled data fidelity. This part of the architecture ensures that each ADC gets just enough time for sampling of the signal and that these time durations are non-overlapping.

The Proposed solution also provides a fair limit on the number of ADCs depending on the input RC sampling time numbers of the input channel and the input signal frequency. This is to ensure that the hardware maintains its accuracy of the data.

To obtain a throughput of nMsps through ADCs having 1Msps throughput each, n ADCs need to work in tandem; basically a signal sampled after every 80 clock cycles will be sampled using n ADCs with an overlap time of sampling phase T given by the equation:



So in such a system each ADC starts sampling 80/n clock cycles after the previous ADC. For example, for n=4 after 20 cycles, for n=8 after 10 cycles, for n=16 after 5 cycles and so on. But the problem with this is the overlap time of sampling phases causing degradation in SNR in individual ADCs as well as pipelined ADC method.

With only the skew generation logic, the problem of simultaneous sampling is not solved and when one ADC is already sampling the data and another ADC begins sampling it, a glitch is observed in the sampled data of the first ADC.

 First Page Previous Page 1 • 2 • 3 Next Page Last Page


Want to more of this to be delivered to you for FREE?

Subscribe to EDN Asia alerts and receive the latest design ideas and product news in your inbox.

Got to make sure you're not a robot. Please enter the code displayed on the right.

Time to activate your subscription - it's easy!

We have sent an activate request to your registerd e-email. Simply click on the link to activate your subscription.

We're doing this to protect your privacy and ensure you successfully receive your e-mail alerts.


Add New Comment
Visitor (To avoid code verification, simply login or register with us. It is fast and free!)
*Verify code:
Tech Impact

Regional Roundup
Control this smart glass with the blink of an eye
K-Glass 2 detects users' eye movements to point the cursor to recognise computer icons or objects in the Internet, and uses winks for commands. The researchers call this interface the "i-Mouse."

GlobalFoundries extends grants to Singapore students
ARM, Tencent Games team up to improve mobile gaming


News | Products | Design Features | Regional Roundup | Tech Impact