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Test method for synchronising multiple GSPS ADCs

30 Jan 2015  | Shane Foss,Rob Reeder

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The AD9625 uses subclass 1 which is critical to how this method of synchronisation is performed. Subclass 1 uses a SYSREF signal for aligning the serial output data. The SYSREF signal essentially gets clocked into the output data of the converter, this arrangement allows for the SYSREF to be synchronous to the conversion clock and ensures that each distributed SYSREF signal arrives at each converter at the same time. This generates a marker or time stamp to be placed in the JESD204B serial output data showing the exact point where the synchronised data analysis should start.

The AD9625 provides two options for using this marker. The designer can use a separate control bit which is part of the entire 16 bit JESD word or replace the LSB of the converter with the SYSREF time-stamp. It should be noted that the test described in this paper used the LSB option. It is also important to note that implementation of these control bits and the manner in which these are used to synchronise multiple converters is not part of the JESD specification. The designation of each control bit in a JESD word is left to the discretion of each individual converter design and may vary from converter to converter.


The test setup
The setup in figure 1 shows how to synchronise two converters. In theory, however, there is no limit to the number of converters that can be synchronised. Starting with a properly designed AD9625 board, as shown in figure 2 and 3, the test setup requires the following equipment.


 • (2) standard desktop/laptop computer running windows operating system
 • (2) Xilinx VC707 development kits
 • (2) AD9625 FMC board, PN: AD-FMCADC2-EBZ
 • Tektronix HFS 9009, pulse generator and stimulus system
 • Rohde & Schwarz SMA 100 A signal generator w/ option B22, low phase noise option
 • 24GHz matched RF cables for the clock and SYSREF connections


Figure 1: A block diagram of the test setup and its major interconnects.


Figure 2: AD9625 FMC board w/ synchronisation connections (PN: AD-FMCADC2-EBZ).


Figure 3: AD-FMCADC2-EBZ connected to FMC1, HPC slot on the VC707 Xilinx Development.


The signal generator (SMA 100 A) provides the 2.5GHz sampling clock for each converter. A single output was then split into two clocks by using a 5350-244ps Pulse Labs power divider. From the two divided outputs a pair of phase and length matched cables are then connected to each AD9625 board. This ensures that the clock will be synchronous when arriving at each converter.

The task of the pulse generator (HFS 9009) is to generate the SYSREF signals. The pulse generator was specifically chosen for this task because it provided multiple differential outputs with reasonably low jitter and the ability to skew one differential output relative to another differential output allowing for the ability to move the placement of the SYSREF signal relative to the sampling clock as needed to ensure setup and hold times were not violated.

Next the analogue input must also be split in the same way as the sample clock. Using another power divider with a pair of phased matched cables to ensure both analogue input signals arrive at each converter's input at the same in time.

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