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Overcome timing challenges for serial flash interface

27 Jan 2015  | Deboleena Sakalley, Snehlata Gutgutia, Prateek Gupta

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Describing the terms used in figures 2-4
SCKq is the clock from the controller's end, SCKf is the clock when it is received at the flash's end. The controller drives the data DOq to the flash, after the propagation delay and the pad delay, the data at the flash interface is DOf. Flash samples this data and drives data to the controller, DIq. After the propagation delays, board and pad delays, the data DIf reaches the controller.


Timing parameters to be considered in SDR mode for flash input timing taken from reference edge A-

t1 (Maximum data delay from the controller to the flash) = tDVO + tDO, Board

t2 (Time at which data is required at flash interface) = ½ clock period+ clock skew – tSU,SDR

t3 (Maximum time for which the data will remain valid at flash) = t1 + one clock period

t4 (Hold requirement of the flash as seen from ref. edge A) = Clock skew + ½ clock period + tDH,SDR


Timing parameters to be considered in SDR mode for flash output timing taken from reference edge C' and capture edge D-

t5 (Total data delay for the data released by flash to be captured at the controller interface) = tV + tDI, Board

t6 (Time at which the data is required at controller's interface) = tSC/2- clock skew—tctrl,setup

t7 (Maximum time for which the flash data at the controller will remain valid) = tSC/2—clock skew + tHO

t8 (Hold requirement of the controller as seen from ref. edge C') = tSC/2—clock skew + tctrl,hold

For timing closure in SDR mode the following equations should be satisfied,

t2 > t1 , this will ensure that the setup requirement of the flash to capture data is met

t3 > t4 , this will ensure that the hold requirement of the flash to capture data is met

t6 > t5 , this will ensure that the setup requirement of the controller to capture data is met

t7 > t8 , this will ensure that the hold requirement of the controller to capture data is met


DDR timing
The increasing requirement of improved throughput has introduced the double data rate (DDR) mode. In DDR mode, the data is transferred on both the rising and falling edges of the clock signal. The DDR serial flashes sample as well as drive the data on both rising and falling edges of flash clock. The path is therefore of only half clock cycle, as a result of which meeting timing in high frequency DDR mode becomes a challenge.

As the maximum data valid time (tv) approaches half clock period, closing the static timing analysis becomes a nightmare since most flashes don't provide a decent output hold time (tHO). As a result the valid data window for timing closure becomes very small as compared to SDR mode. In absence of any sort of data learning it becomes very difficult to assure timing at maximum frequency for DDR mode across PVT corners. Figure 3 shows the delays to be considered for closing the timing in DDR mode.


Figure 3: DDR timing requirement.



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