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Burn-in test: Stressing of redundant memory bits

28 Jan 2015  | Mayank Parasrampuria, Neetin Singh

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Burn-in stressing of an SoC comes with a few drawbacks, one of them being non-uniform stressing of logic. Here we will discuss non-uniform stressing of memory.

Devices, when under burn-in stressing, can have repaired or non-repaired memories. If device has a repaired memory then only the selected redundant columns (or rows) of memory will be accessed during the burn-in stress and the un-used remaining redundant columns (or rows) will not be accessed which will leave certain portion of memory un-stressed. Similar is the case with a non-repaired memory, here all the redundant columns (or rows) are left un-stressed. This translates into inability to repair a device after burn-in and infield repair. If repair (after burn-in or infield) is attempted, it will expose an un-stressed logic, which means reliability concerns.


Design change
A circuit which get active during Memory BIST burn-in mode and enables the access to every redundant column or row) of memory during the burn-in run. By this circuit uniform stressing of all redundant columns (or rows) is achieved.

The proposed circuit has the following components:

1. Event detector: detects the completion of selected March Algorithm run of Memory BIST during BURNIN.

2. Repair data logic controller: Changes the data loaded into the repair data register after completion of each full Memory BIST run to ensure a uniform stress distribution.

Repair information is loaded by Memory BIST controller from the fuse or flash into the repair data register which enable the replacement of faulty column (or row) with the redundant columns (or rows) in-order to repair a device.

During the Memory BIST burn-in stressing, the BIST is set to run in an infinite loop, here the event detector detects the completion of selected MARCH Algorithm run and with each run completion its generates a trigger which goes to repair data calculator and changes the selected column (or row) as faulty and resulting in removing it from test for that run. This process repeats for each run, selecting a new column (or row) as faulty. This process results in applying a uniform stress on the memory during the process.


Conclusion
With the above proposed circuitry in place, we can ensure that during burn-in stressing of memories the entire memory array is uniformly stressed. This circuit does not require any change in in memory design or Memory BIST logic, so is easy to implement.

Additionally this is a fully automated process (achieved via hardware), which does not require any input or control from outside the device, which fits well with the burn-in tester requirements of minimum interactions during testing.


About the authors
Mayank Parasrampuria and Neetin Singh contributed this article.




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