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eInfochips reveals eMMC 5.0 verification IP

10 Feb 2015

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eInfochips has recently unveiled its eMMC 5.0 verification IP (VIP) that aims to speed up RTL verification cycles of JEDEC-compliant devices for mobiles, tablets and other consumer devices. Promising to the reliability and performance of next-generation embedded flash memory systems, the company also offers ASIC and FPGA verification services for companies in the storage industry.

The eMMC 5.0 standard from JEDEC (JESD84-B50) will improve data throughput from 1.6Gb/s to 3.2Gb/s (over previous standards), improving memory access speeds for consumer devices, stated the company. The architecture encompasses the flash memory and its controller on a single IC package for use as an embedded non-volatile memory system (NVMS).

The eMMC 5.0 VIP enables design and verification engineers to extensively test the functionality of embedded memory systems. Verification Models and Compliance Test Suites are developed in SystemVerilog (SV) and support UVM environment. The verification architecture includes key modules such as the host controller and the eMMC device controller.

The VIP bundles in deliverables like Sample Use Cases, Sanity Test Cases, Verification Environment (to be integrated) and the User Guide.

The eMMC 5.0 VIP is available now to select customers.




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