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Performing memory test with a slow clock

19 Mar 2015  | Martin Keim

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Recently, I was involved in supporting a memory built-in self-test (MBIST) user. Because of an error in the design, the engineer couldn't run a memory test because the high-speed system clock wasn't available. In this case, only the relatively slow test clock was available. Of course, the user was very concerned about the quality of the memory test and was even more concerned about the potential increased defective parts per million (DPPM) number of his product. Fortunately, most memory tests aren't dependent on the high-speed clock signal.

Using a slow-speed clock, the chance of detecting memory defects reduces very little, which results in slightly higher DPPM levels. Whether this higher DPPM level is significant for the product depends more on the product's application than on the test. For automotive or medical products, even the slightest increase in DPPM is unacceptable, but the same DPPM increase for low-cost consumer electronics might very well be within the contractual obligations.

The ability of modern memories to self-time is at the core of the mystery. Self-timing is the ability to execute a read or write operation at a certain speed without dependency on an external clock stimuli. The time starts when a change of certain memory control input ports signal the start of a read or write operation. The time then stops when the operation is complete.

There are two important paths in the memory that determine the test: the path the data needs to take and the self-timing path. The purpose of the self-timing path is to always produce the same delay, within margins, and then trigger the sensing of the data coming out of the memory array. Together, these paths set the speed at which a system's memory operates reliably.

To be precise for the context here, synchronous, embedded Static Random Access Memory (SRAM), used in today's microelectronics, are virtually all self-timed. The figure depicts a self-timed memory. The blocks and gates shaded grey are the key components of the self-timing feature. The delay through the Model Row and Column Decode logic determines how long the write drivers are turned on during a write operation and when the latches should capture the output of the sense amplifiers during a read operation, after the occurrence of a rising clock edge. Once the operation is complete, the address precoders are reset and the bit lines are precharged in preparation for the next memory access.


Figure: Diagram of a self-timed memory.


Memory test algorithms, like the so-called "Serial March" algorithm, are essentially a very specific sequence of writing to and reading from memory cells. For example, such a memory test algorithm may write a logic 1 into cell "a," then write a logic 0 into cell "b." If everything is OK, reading from cell "a" should result in a 1. Reading a 0 indicates a defect.

If the time that a read or write operation takes depends only on the memory itself, why do we need a high-speed clock in the first place? The speed of the clock becomes important for the MBIST logic itself. That is, it determines the speed at which the test logic can fire off these read and write commands at consecutive clock cycles towards the memory. That creates a specific sequence of operations, which forms the memory-test algorithm.

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