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Minimising PDN impedance at high frequencies

17 Apr 2015  | Chang Fei Yee

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The hardware designer should consider using smaller capacitor package size (0402 or smaller) or HDI (high density interconnect) PCB technology in order to fit all decoupling capacitors directly under the BGA IC to achieve minimum loop inductance and PDN impedance.


Figure 3: Decoupling capacitors (PCB bottom layer) partially placed under BGA IC (PCB top layer).


Figure 4: All decoupling capacitors (PCB bottom layer) placed under BGA IC (PCB top layer).


Figure 5: PDN impedance based on effect of loop inductance.


Thinner substrate between power and ground planes
By applying a thinner dielectric between power and ground planes, not only is loop inductance reduced, but also plane capacitance is increased, as governed in equation (2), which in turn results a lower PDN impedance.


C = ε A / d (2)

C = plane capacitance

ε = substrate property

A = overlapped conductive area between power and ground planes

d = substrate thickness between power and ground planes


The effect of substrate thickness is studied by conducting post-layout PI analysis on PCB with stackup shown in figure 6, where power net of interest is laid out on layer 6, with reference to ground plane on layer 8. Substrate thickness between layer 6 and 8 is plotted for 10 mils 30 mils (figure 7).


Figure 6: Stackup of example PCB.


Figure 7: PDN impedance variation with substrate thickness.



Conclusion
Proper decoupling capacitor placement and stackup planning are crucial to obtaining a low PDN impedance at high frequencies.


References
[1] "Power Distribution Network Planning", by Barry Olney, In-Circuit Design Pty Ltd Australia

[2] "Basic Concepts of Power Distribution Network Design for High Speed Transmission", by F.Carrio, V.Gonzalez and E.Sanchis

[3] High-Density Interconnect. http://www.ami.ac.uk/courses/topics/0262_hdi/


About the author
Chang Fei Yee has been working in Agilent's Electronic Measurement Group (renamed as Keysight after 1 Aug 2014) since 2006 with experience in embedded system HW design, multi-Gigabit backplane design, signal integrity, power integrity, EMI and jitter/phase noise analysis.


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