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Mitigating SEU using isolated design flow (Part 1)

19 May 2015  | Rajan Bedi

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Figure 4: Here is the implemented, isolated design. (Image courtesy of Xilinx).


The next article in this series will demonstrate the use of Xilinx's Isolated-Design Flow within the latest release of Vivado IDE, 2015.1. The Soft-Error Mitigation (SEM) IP allows space users to assess the criticality of SEUs on the implemented design, with fault injection of configuration memory allowing users to characterise and manage SEFI behaviour. Logic partitioning offers the potential to protect against SEUs increasing device availability and overall system reliability.

On the subject of soft errors, one of our colleagues, Maxim Malyy, from the Quazar Space Company based in St. Petersburg, Russia, is considering using a highly-elliptical orbit to characterise the radiation sensitivity of components. The dose and nature of the Van-Allen belts is not fully understood and cyclotrons are not truly representative of the harsh environment of space. Quazar's complementary approach of using a 3U, CubeSat platform in HEO, together with redundancy and passive z-shielding to understand the radiation sensitivity of a payload, will improve knowledge for its customers as well as our industry. What are your views on Quazar's plans?

Until next time, stay SEE free!


About the author
Rajan Bedi is currently CEO of Spacechips. Rajan worked at Astrium (now Airbus) for twelve years developing and researching space-grade electronics for telecommunication, navigation, Earth-observation and science missions. As Head of the Mixed-Signal Design Group, Rajan's team developed the hardware for the award-winning, channelising payload currently operating on-board the Alphasat telecommunication satellite.


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