# Simple way to develop Spice macro models (Part 2)

26 May 2015 | Soufiane Bendaoud**Share this page with your friends**

In part 2, we will look at a different topology: a CMOS (rail-to-rail) input and output. The parameters you need to develop your macro model are the same as in part 1, as well as the three-stage topology: input, middle and rail-to-rail swing stages. Since we covered the CMOS output stage in part 1, we will focus on the input stage.

The highlighted equations are to be inserted into the netlist. Equations in blue are for your own observation purposes. The ones in red may be required in the model parameters at the end of the netlist.

**Rail-to-rail input stage**

Unlike the non-rail-to-rail input stage, you will need two differential pairs of MOSFETs. Just like in the bipolar input stage, you have the option to add degeneration drain resistors (RS) at the expense of the gain in the first stage.

We can assume that the design goes 0.3V beyond the positive rail and –0.3V in the other direction. Now the Vcm high is 5.3 from a 5-V single supply, and the Vcm low is 0.3V below ground.

Next, compute the total noise contribution (referred to input [RTI]) from the input differential pairs and RDs (and emitter degeneration or REs, if applicable).

The total RTI noise is expressed as:

en_{total=}sqrt(enR_{D}N^{2}+en_{NMOS}^{2}+enR_{D}P^{2}+ en_{PMOS}^{2})

where

enR_{D}N=sqrt((2*4*k*T*R_{D3,4})/(2*Avin)),

enR_{D}P=sqrt((2*4*k*T*R_{D1,2})/(2*Avin)),

and k is Boltzmann's constant, and T is the temperature in Kelvin.

en_{NMOS}=sqrt((2*Id_{N}*R_{D3,4})/(2*Avin))

en_{PMOS}=sqrt((2*Id_{P}*R_{D1,2})/(2*Avin))

Id_{N}=sqrt(4*k*T*2R_{D3,4}/3)

Id_{P}=sqrt(4*k*T*2R_{D1,2}/3)

Just as in the bipolar input design, set the input stage gain as:

Avin=Aol/Avout*Avmiddle

Next, address the device parameters needed in the netlist for the NMOS pair and PMOS pair. Set Lambda=0.01, Kp=1E-5 in A/V^{2} and I2=1e-3A. Do exactly the same for the PMOS pair, and call the tail current I1 instead of I2.

You can always change the value of these parameters. For example, if you're trying to get a lower tail current, try setting I2 to 100µA, if you are willing to accept a higher noise contribution from RDs.

Now that the current is set, you can compute:

R_{D3,4}=V_{RD}*2/I2 and R_{D1,2}=V_{RD}*2/I1

W/L_{3,4}=2*Avin/2*R_{D3,4}*I2*kp

W/L_{1,2}=2*Avin/2*R_{D1,2}*I1*kp

Set C2=C1 for the NMOS and PMOS pairs, respectively, and write:

C2=1/(2* R_{D3,4}*p1)

where p1=GBP/tan(90-ɸm-2) is in radians.

The transconductances gm1 and gm2 for the PMOS and NMOS are expressed as:

Sqrt(I2*kp*W/ L_{3,4}) and Sqrt(I1*kp*W/ L_{1,2})

In order to set the proper common-mode input-voltage range, set up:

V2=V_{CMlow}+0.7-sqrt(I2/kp*W/L_{3,4})-V_{T2} and VT2=V_{CMhigh}+0.5*I2*RD_{3,4}-Vs

where Vs is the supply voltage.

Because we have two differential pairs (NMOS and PMOS), you also need to set up:

V1=Vs-V_{CMhigh}+0.7-sqrt(I1/kp*W/L_{1,2})+V_{T1} and V_{T1}=V_{CMlow}-0.5*I2*R_{D1,2}

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