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Digital filter simulation with PSpice

27 May 2015  | Dobromir Dobrev

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The PSpice schematic for AC simulation of a digital moving-average filter is shown in figure 1. The moving-average filters reject any signals with frequencies in the filter zeros.

For example, let the sampling frequency be fs = 2kHz, or T = 0.5ms. To reject 50Hz power-line (PL) interference, the samples from one period must be averaged. At 2kHz sampling rate, one PL period consists of 20ms/0.5ms = 40 samples. The averager can be simulated directly by a transfer function (output MAV40T), or by a structure close to its real algorithmic realisation using delay blocks, gain blocks, and summing and difference junctions (output MAV40R). The simulation has notches at all harmonics of PL interference, as seen in figure 2.


Figure 1: PSpice schematic for AC line interference averager (comb filter).


Figure 2: Frequency response of the averager.


The presented approach is fast and easy. I have used it for 10 years, and was inspired to share my knowledge after discovering the Design Idea in Reference 1. Other examples of digital filters simulated with the presented approach can be found in Reference 2.


References
1. Lopez D., Transmission lines simulate digital filters in PSpice, EDN, 2008

2. http://www.researchgate.net/profile/Dobromir_Dobrev/publications


About the author
Dobromir Dobrev has about 20 years experience in CMOS and BJT analogue and mixed-signal IC design (opamps, comparators, bandgaps, ldos, filters, oscillators, lvdss, plls, adcs, etc.), as well as in signal processing in medical electronics (bioinstrumentation, bioamplifiers, biosignal filtering) where he has many publications. He started working at the Central Laboratory for Electromedical Instrumentation (CLEMA) in a former Medical Academy Sofia. He received his PhD degree in Electronics from the Centre of Biomedical Engineering at the Bulgarian Academy of Sciences in 2001. Since 1997 he continued his career mainly in the field of microelectronics. He was an analogue IC designer at Semcotec Engineering, Silway Semiconductors, Megaxess and a senior IC designer at Melexis. Currently, he is with FACET (Fabless Centre for Engineering and Test), and lives in Sofia, Bulgaria.


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